外文文獻(xiàn)及翻譯----ds1820_單總線數(shù)字溫度計(jì)

1、<p>　　DS1820 單總線數(shù)字溫度計(jì)</p><p>　　DSl820數(shù)字溫度計(jì)提供9位(二進(jìn)制)溫度讀數(shù)指示器件的溫度Information is sent to/from the DS18B20 over a 1-Wire interface, so that only one wire (and ground) needs to be connected from a central mic

2、roprocessor to a DS18B20.。信息經(jīng)過(guò)單線接口送入DSl820或從DSl820送出因此從主機(jī)CPU到DSl820僅需一條線(和地線)。 Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external powe

3、r source.寫(xiě)數(shù)據(jù)，讀溫度轉(zhuǎn)換可以由數(shù)據(jù)線本身來(lái)提供電源而不需要一個(gè)外部電源。由于每個(gè)DS18B20的包含一個(gè)唯一的序列號(hào)，因此任意多個(gè)DSl820可以存放在同一條單線總線上。這允許在不同的地方放置溫度傳感器。此</p><p>　　1OVERVIEW綜述</p><p>　　The block diagram of Figure 1 shows the major componen

4、ts of the DS18B20.DS18B20的有四個(gè)主要的數(shù)據(jù)部分組成：1）64位激光ROM，2）溫度靈敏元件，3）非易失性溫度報(bào)警觸發(fā)器TH和TL，4）配置寄存器。器件從單線的通信線上取得其電源，在信號(hào)線為高電平的時(shí)間周期內(nèi)，把能量貯存在內(nèi)部的電容器中，在單信號(hào)線為低電平的時(shí)間期內(nèi)斷開(kāi)此電源，直到信號(hào)線變?yōu)楦唠娖街匦陆由霞纳娙蓦娫礊橹埂Ｗ鳛榱硪环N可供選擇的方法，DS1820 也可用外部5V 電源供電。</p>&

5、lt;p>　　與DS1820 的通信經(jīng)過(guò)一個(gè)單線接口。在單線接口情況下，在ROM 操作未定建立之前不能使用存貯器和控制操作。主機(jī)必須首先提供五種ROM 操作命令之一：1）Read ROM(讀ROM)， 2）Match ROM(符合ROM)，3）Search ROM(搜索ROM)，4）Skip ROM(跳過(guò)ROM)，或5） Alarm Search(告警搜索)。 這些命令對(duì)每一器件的64 位激光ROM 部分進(jìn)行操作。如果在單線上有許

6、多器件，那么可以挑選出一個(gè)特定的器件，并給總線上的主機(jī)指示存在多少器件及其類型。在成功地執(zhí)行了ROM 操作序列之后，可使用存貯器和控制操作，然后主機(jī)可以提供六種存貯器和控制操作命令之一。</p><p>　　一個(gè)控制操作命令指示DS1820 完成溫度測(cè)量。該測(cè)量的結(jié)果將放入DS1820 的高速暫存存貯器（Scratchpad memory）。通過(guò)發(fā)出讀暫存存儲(chǔ)器內(nèi)容的存儲(chǔ)器操作命令可以讀出此結(jié)果。每一溫度告警觸發(fā)

7、器TH 和TL 構(gòu)成一個(gè)字節(jié)的EEPROM， 如果不對(duì)DS1820 施加告警搜索命令，這些寄存器可用作通用用戶存儲(chǔ)器，使用存儲(chǔ)器操作命令可以寫(xiě)TH 和TL。對(duì)這些寄存器的訪問(wèn)是通過(guò)高速暫存存儲(chǔ)器，所有數(shù)據(jù)均以最低有效位在前的方式被讀寫(xiě)PARASITE POWER。</p><p><b>　　2 寄生電源</b></p><p>　　寄生電源電路當(dāng)I/O或VDD引腳為

8、高電平時(shí)，這個(gè)電路便“取”得電源。只要符合指定的定時(shí)和電壓要求，I/O將提供足夠的功率，寄生電源的優(yōu)點(diǎn)是雙重的：1）利用此引腳，遠(yuǎn)程溫度檢測(cè)無(wú)需本地電源，2）缺少正常電源條件下也可以讀ROM。In order for the DS18B20 to be able to perform accurate temperature conversions, sufficient power must be provided over the

9、DQ line when a temperature conversion is taking place.。。。。</p><p>　　為了使DS1820 能完成準(zhǔn)確的溫度變換，當(dāng)溫度變換發(fā)生時(shí)，I/O線上必須提供足夠的功率。因?yàn)镈S1820的工作電流高達(dá)1mA，5K 的上拉電阻將使I/O線沒(méi)有足夠的驅(qū)動(dòng)能力。如果幾個(gè)SD1820 在同一條I/O 線上而且企圖同時(shí)變換，那么這一問(wèn)題將變得特別尖銳。</p&

10、gt;<p>　　There are two ways to assure that the DS18B20 has sufficient supply current during its active conversion cycle.有兩種方法確保DS1820在其有效變換期內(nèi)得到足夠的電源電流。The first is to provide a strong pullup on the DQ line wheneve

11、r temperature conversions or copies to the E 2 memory are taking place.第一種方法是發(fā)生溫度變換時(shí)在I/O線上提供一強(qiáng)的上拉電阻，This may be accomplished by using a MOSFET to pull the DQ line directly to the power supply as shown in Figur通過(guò)使用一個(gè)MOSFE

12、T把I/O線直接拉到電源可達(dá)到這一點(diǎn)，當(dāng)使用寄生電源方式時(shí)VDD引腳必須連接到地。</p><p>　　Another method of supplying current to the DS18B20 is through the use of an external power supply tied to the V DD pin, as shown in Figure 3.向DS1820 供電的另外一種

13、方法是通過(guò)使用連接到VDD 引腳的外部電源，這種方法的優(yōu)點(diǎn)是在I/O 線上不要求強(qiáng)的上拉電阻，總線上主機(jī)不需向上連接便在溫度變換期間使線保持高電平，這就允許在變換時(shí)間內(nèi)其它數(shù)據(jù)在單線上傳送。此外，在單線總線上可以放置任何數(shù)目的DS1820 ，而且如果它們都使用外部電源，那么通過(guò)發(fā)出跳過(guò)（Skip）ROM 命令和接著發(fā)出變換（Convert）T 命令，可以同時(shí)完成溫度變換。注意只要外部電源處于工作狀態(tài)，GND（地）引腳不可懸空。 <

14、/p><p>　　For situations where the bus master does not know whether the DS18B20s on the bus are parasite powered or supplied with external V DD , a provision is made in the DS18B20 to signal the power supply sch

15、eme used.在總線上主機(jī)不知道總線上DS1820 是寄生電源供電還是外部VDD 供電的情況下，在DS1820 內(nèi)采取了措施來(lái)通知采用的供電方案?？偩€上主機(jī)通過(guò)發(fā)出跳過(guò)（Skip）ROM 的操作約定，然后發(fā)出讀電源命令，可以決定是否有需要在DS1820 的總線上放置上拉電阻。在此命令發(fā)出后，主機(jī)接著發(fā)出讀時(shí)間片。如果是寄生供電，DS1820 將在單線總線上送回（0）；如果由VDD 引腳供電，它將送回（1）。如果主機(jī)接收到一個(gè)（0），

16、它知道它必須在溫度變換期間在I/O 線上供一個(gè)強(qiáng)的上拉。</p><p>　　3 OPERATION - ALARM SIGNAL3運(yùn)算-報(bào)警信號(hào)</p><p>　　After the DS18B20 has performed a temperature conversion, the temperature value is compared to the trigger value

17、s stored in TH and TL.在DS1820 完成溫度變換之后，溫度值與貯存在TH和TL內(nèi)的觸發(fā)值相比較，因?yàn)檫@些寄存器僅僅是8位，所以0.5度在比較時(shí)被忽略。TH或TL的最高有效位直接對(duì)應(yīng)于16位溫度寄存器的符號(hào)位，如果溫度測(cè)量的結(jié)果高于TH或低于TL，那么器件內(nèi)告警標(biāo)志將置位。每次溫度測(cè)量將更新告警標(biāo)志，只要告警標(biāo)志置位，DS1820 將對(duì)告警搜索命令做出響應(yīng)。這允許并聯(lián)連接許多DS1820，同時(shí)進(jìn)行溫度測(cè)量，如果某處

18、溫度超過(guò)極限，那么可以識(shí)別出正在告警的器件并立即將其讀出而不必讀出非告警的器件。</p><p>　　4 64-BIT LASER4 44444464位激光ROM</p><p>　　Each DS18B20 contains a unique ROM code that is 64-bits long.每一DS1820包括一個(gè)唯一的64位長(zhǎng)的ROM編碼，開(kāi)始的8位是單線產(chǎn)品系列編碼（DS

19、1820編碼是10h），接著的48位是唯一的系列號(hào)，最后的8位是開(kāi)始56位CRC，64位ROM和ROM 操作控制部分允許DS1820 作為一個(gè)單線器件工作并遵循“單線總線系統(tǒng)”的單線協(xié)議，直到ROM 操作協(xié)議被滿足，DS1820 控制部分的功能是不可訪問(wèn)的。單線總線主機(jī)必須首先操作五種ROM 操作命令之一：1）Read ROM(讀ROM)，2）Match ROM(匹配ROM)，3）Search ROM(搜索ROM)，4）Skip ROM

20、(跳過(guò)ROM)，或5）Alarm Search（告警搜索）。在成功地執(zhí)行了ROM操作序列之后，DS1820 特定的功能便可訪問(wèn)，然后總線上主機(jī)可提供六個(gè)存貯器和控制功能命令之一。 </p><p>　　5CRC GENERATION CRC生成</p><p>　　The DS18B20 has an 8-bit CRC stored in the most significant byt

21、e of the 64-bit ROM. The bus master can compute a CRC value from the first 56-bits of the 64-bit ROM and compare it to the value stored within the DS18B20 to determine if the ROM data has been received error-free by the

22、bus master. The equivalent polynomial function of this CRC is:DS1820 有一存貯在64 位ROM 的最高有效字節(jié)內(nèi)的8 位CRC?？偩€上的主機(jī)可以根據(jù)64 位ROM 的前56 位計(jì)算機(jī)CRC 的值并把它與存貯在DS1820 內(nèi)的值進(jìn)行比較以決定ROM 的數(shù)據(jù)是否已被主機(jī)正確地接收。CRC 的等效多項(xiàng)式函數(shù)為：</p><p>　　CRC = X 8

23、 + X 5 + X 4 + 1</p><p>　　The DS18B20 also generates an 8-bit CRC value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of data bytes.DS1820

24、也利用與上述相同的多項(xiàng)式函數(shù)產(chǎn)生一個(gè)8 位CRC值并把此值提供給總線的主機(jī)以確認(rèn)數(shù)據(jù)字節(jié)的傳送，在使用CRC來(lái)確認(rèn)數(shù)據(jù)傳送的每一種情況中，總線主機(jī)必須使用上面給出的多項(xiàng)式函數(shù)計(jì)算CRC的值并把計(jì)算所得的值，或者與存貯在DS1820的64位ROM部分中的8位CRC值（ROM讀數(shù)），或者與DS1820 中計(jì)算得到的8位CRC值（在讀暫存存貯器中時(shí)它作，為第九個(gè)字節(jié)被讀出），進(jìn)行比較。CRC 值的比較和是否繼續(xù)操作都由總線主機(jī)來(lái)決定，當(dāng)存貯在

25、DS1820 內(nèi)或由DS1820 計(jì)算得到的CRC 值與總線主機(jī)產(chǎn)生的值不相符合時(shí)，在DS1820 內(nèi)沒(méi)有電路來(lái)阻止命令序列的繼續(xù)執(zhí)行。(which is read as a ninth byte </p><p>　　總線CRC 可以使用一個(gè)移位寄存器和“異或”（XOR）門(mén)組成的多項(xiàng)式產(chǎn)生器來(lái)產(chǎn)生，其它有關(guān)Dallas 公司單線循環(huán)冗余校驗(yàn)的信息可參見(jiàn)標(biāo)題為“理解和使用Dallas 半導(dǎo)體公司接觸式存貯器產(chǎn)品”

26、的應(yīng)用注釋移。位寄存器的所有位被初始化為零，然后從產(chǎn)品系列編碼的最低有效位開(kāi)始，每次移入一位。當(dāng)產(chǎn)品系列編碼的8 位移入以后，接著移入序列號(hào)。在序列號(hào)的第48 位進(jìn)入之后，移位寄存器便包含了CRC值。移入CRC的8 位應(yīng)該使移位寄存器返回至全零。</p><p><b>　　6 MEMO存儲(chǔ)器</b></p><p>　　溫度傳感器DS1820 的存貯器由一個(gè)高速暫存

27、便箋式RAM和一個(gè)非易失性電可擦除E2RAM組成，后者存貯高溫度和低溫度和觸發(fā)器TH和TL。暫存存貯器有助于在單線通信時(shí)確保數(shù)據(jù)的完整性，數(shù)據(jù)首先寫(xiě)入暫存存貯器，在那里它可以被讀回。當(dāng)數(shù)據(jù)被校驗(yàn)之后，復(fù)制暫存存貯器的命令把數(shù)據(jù)傳送到非易失性E2RAM。這一過(guò)程確保了更改存貯器的時(shí)候保持?jǐn)?shù)據(jù)的完整性。The scratchpad is organized as eight bytes of memory.。。。。。。。。。。。。。<

28、/p><p>　　暫存存貯器是按8位字節(jié)存儲(chǔ)器來(lái)組織的，頭兩個(gè)字節(jié)包含測(cè)得溫度信息，第三和第四個(gè)字節(jié)是TH和TL的易失性拷貝，在每一次上電復(fù)位時(shí)被刷新。接著的兩個(gè)字節(jié)沒(méi)有使用，但是在讀回時(shí)，它們呈現(xiàn)為邏輯全1。第七字節(jié)和第八個(gè)字節(jié)是計(jì)數(shù)寄存器，它們可用于獲得較高的溫度分辨率。還有第九個(gè)字節(jié)它可用Read Scratchpad（讀暫存存貯器）命令讀出，該字節(jié)包含一個(gè)循環(huán)冗余校驗(yàn)（CRC）字節(jié)，它是前面所有8個(gè)字節(jié)的CR

29、C值，此CRC值以（CRC產(chǎn)生）一節(jié)中所述的方式產(chǎn)生。</p><p>　　7 READ/WRITE TIME SLO7讀/寫(xiě)時(shí)隙</p><p>　　7.1Write Time Slots寫(xiě)時(shí)隙 </p><p>　　當(dāng)主機(jī)把數(shù)據(jù)線從高邏輯電平拉至低邏輯電平時(shí)，產(chǎn)生寫(xiě)時(shí)間片。有兩種類型的寫(xiě)時(shí)間片：寫(xiě)1時(shí)間片和寫(xiě)0時(shí)間片，所有時(shí)間片必須有最短為60 us的持續(xù)期，在

30、各寫(xiě)周期之間必須有最短為1us的恢復(fù)時(shí)間。在I/O 線片由高電平變?yōu)榈碗娖街?，DS1820 在15us 至60us 的窗口之間對(duì)I/O 線采樣。如果線為高電平，寫(xiě)1就發(fā)生。如果線為低電平，便發(fā)生寫(xiě)0。對(duì)于主機(jī)產(chǎn)生寫(xiě)1時(shí)間片的情況，數(shù)據(jù)線必須先被拉至邏輯低電平，然后就被釋放，使數(shù)據(jù)線在寫(xiě)時(shí)間片開(kāi)始之后的15 us之內(nèi)拉至高電平。對(duì)于主機(jī)產(chǎn)生寫(xiě)0時(shí)間片的情況，數(shù)據(jù)線必須被拉至邏輯低電平且至少保持低電平60 us。</p>&

31、lt;p>　　7.2Read Time Slots讀時(shí)隙 </p><p>　　當(dāng)從DS1820 讀數(shù)據(jù)時(shí)，主機(jī)產(chǎn)生讀時(shí)間片段。當(dāng)主機(jī)把數(shù)據(jù)線從邏輯高電平拉至低電平時(shí)，產(chǎn)生讀時(shí)間片，數(shù)據(jù)線必須保持在低邏輯電平至少1 us；來(lái)自DS1820 的輸出數(shù)據(jù)在讀時(shí)序下降沿后15us有效。因此，為了讀出從讀時(shí)間片開(kāi)始算起15us的狀態(tài)主機(jī)必須停止把I/O引腳驅(qū)動(dòng)至低電平。在讀時(shí)間片結(jié)束時(shí)，I/O 引腳經(jīng)過(guò)外部的上拉電

32、阻拉回至高電平。所有讀時(shí)間片的最短持續(xù)期限為60us，各個(gè)讀時(shí)間片之間必須有最短為1us的恢復(fù)時(shí)間。TINRT，TRC 和TSAMPLE 之和必須小于15us。通過(guò)使TINRT和TRC盡可能小且把主機(jī)采樣時(shí)間定在15us期間的末尾，系統(tǒng)時(shí)序關(guān)系就有最大的余地。</p><p>　　DS18B20 Programmable Resolution 1-Wire Digital Thermometer</p>

33、;<p>　　The DS18B20 Digital Thermometer provides 9 to 12-bit (configurable) temperature readings which indicate the temperature of the device. Information is sent to/from the DS18B20 over a 1-Wire interface, so tha

34、t only one wire (and ground) needs to be connected from a central microprocessor to a DS18B20. Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for

35、an external power source. Because each DS18B20 contains a unique silicon s</p><p>　　1 OVERVIEW</p><p>　　The block diagram of Figure 1 shows the major components of the DS18B20. The DS18B20 has f

36、our main data components: 1) 64-bit laser ROM, 2) temperature sensor, 3) nonvolatile temperature alarm triggers TH and TL, and 4) a configuration register. The device derives its power from the 1-Wire communication line

37、by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1-Wire line until it</p><p>　　Communi

38、cation to the DS18B20 is via a 1-Wire port. With the 1-Wire port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five RO

39、M function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. These commands operate on the 64-bit laser ROM portion of each device and can single out a specific device if many are prese

40、nt on the 1-Wire line as well as indicate to the bus </p><p>　　One control function command instructs the DS18B20 to perform a temperature measurement. The result of this measurement will be placed in the DS

41、18B20’s scratch-pad memory, and may be read by issuing a memory function command which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of 1 byte EEPROM each. If the alarm sea

42、rch command is not applied to the DS18B20, these registers may be used as general purpose user memory. The scratchpad also contains a co</p><p>　　2 PARASITE POWER</p><p>　　The block diagram (Fig

43、ure 1) shows the parasite-powered circuitry. This circuitry “steals” power whenever the DQ or VDD pins are high. DQ will provide sufficient power as long as the specified timing and voltage requirements are met (see the

44、section titled “1-Wire Bus System”). The advantages of parasite power are twofold: 1) by parasiting off this pin, no local power source is needed for remote sensing of temperature, and 2) the ROM may be read in absence o

45、f normal power. </p><p>　　In order for the DS18B20 to be able to perform accurate temperature conversions, sufficient power must be provided over the DQ line when a temperature conversion is taking place. Si

46、nce the operating current of the DS18B20 is up to 1.5 mA, the DQ line will not have sufficient drive due to the 5k pull up resistor. This problem is particularly acute if several DS18B20s are on the same DQ and attemptin

47、g to convert simultaneously.</p><p>　　There are two ways to assure that the DS18B20 has sufficient supply current during its active conversion cycle. The first is to provide a strong pull up on the DQ line w

48、henever temperature conversions or copies to the E2 memory are taking place. This may be accomplished by using a MOSFET to pull the DQ line directly to the power supply as shown in Figure 2. The DQ line must be switched

49、over to the strong pull up within 10 us maximum after issuing any protocol that involves copying to the E2 memo</p><p>　　Another method of supplying current to the DS18B20 is through the use of an external p

50、ower supply tied to the VDD pin, as shown in Figure 3. The advantage to this is that the strong pull up is not required on the DQ line, and the bus master need not be tied up holding that line high during temperature con

51、versions. This allows other data traffic on the 1-Wire bus during the conversion time. In addition, any number of DS18B20s may be placed on the 1-Wire bus, and if they all use external power, th</p><p>　　The

52、 use of parasite power is not recommended above 100?C, since it may not be able to sustain communications given the higher leakage currents the DS18B20 exhibits at these temperatures. For applications in which such tempe

53、ratures are likely, it is strongly recommended that VDD be applied to the DS18B20. </p><p>　　For situations where the bus master does not know whether the DS18B20s on the bus are parasite powered or supplied

54、 with external VDD, a provision is made in the DS18B20 to signal the power supply scheme used. The bus master can determine if any DS18B20 are on the bus which require the strong pull up by sending a Skip ROM protocol, t

55、hen issuing the read power supply command. After this command is issued, the master then issues read time slots. The DS18B20 will send back “0” on the 1-Wire bus if i</p><p>　　3 OPERATION - ALARM SIGNALING&l

56、t;/p><p>　　After the DS18B20 has performed a temperature conversion, the temperature value is compared to the trigger values stored in TH and TL. Since these registers are 8-bit only, bits 9-12 are ignored for

57、comparison. The most significant bit of TH or TL directly corresponds to the sign bit of the 16-bit temperature register. If the result of a temperature measurement is higher than TH or lower than TL, an alarm flag insid

58、e the device is set. This flag is updated with every temperature measurement. As </p><p>　　4 64-BIT LASERED ROM</p><p>　　Each DS18B20 contains a unique ROM code that is 64-bits long. The first 8

59、 bits are a 1-Wire family code (DS18B20 code is 28h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. The 64-bit ROM and ROM Function Control section allow the DS18B20 to oper

60、ate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The functions required to control sections of the DS18B20 are not accessible until the ROM function protocol</p>&

61、lt;p>　　5 CRC GENERATION</p><p>　　The DS18B20 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56-bits of the 64-bit ROM and com

62、pare it to the value stored within the DS18B20 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is:</p><p>　　The DS18B20 also genera

63、tes an 8-bit CRC value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of data bytes. In each case where a CRC is used for data transfer validation, the b

64、us master must calculate a CRC value using the polynomial function given above and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the DS18B20 (for ROM reads) or the 8-bit C

65、RC value computed within the DS18B20(</p><p>　　The 1-Wire CRC can be generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 6. Additional information about the

66、 Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products.”</p><p>　　The shift regi

67、ster bits are initialized to 0. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. Af

68、ter the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all 0s.</p><p><b>　　7 MEMORY</b&g

69、t;</p><p>　　The DS18B20’s memory is organized as shown in Figure 8. The memory consists of a scratchpad RAM and a nonvolatile, electrically erasable RAM, which stores the high and low temperature triggers TH

70、 and TL, and the configuration register. The scratchpad helps insure data integrity when communicating over the 1-Wire bus. Data is first written to the scratchpad using the Write Scratchpad command. It can then be verif

71、ied by using the Read Scratchpad command. After the data has been verified, a Copy Sc</p><p>　　The scratchpad is organized as eight bytes of memory. The first 2 bytes contain the LSB and the MSB of the measu

72、red temperature information, respectively. The third and fourth bytes are volatile copies of TH and TL and are refreshed with every power-on reset. The fifth byte is a volatile copy of the configuration register and is r

73、efreshed with every power-on reset. The configuration register will be explained in more detail later in this section of the datasheet. The sixth, seventh, and eighth b</p><p>　　It is imperative that one wri

74、tes TH, TL, and config in succession; i.e. a write is not valid if one writes only to TH and TL, for example, and then issues a reset. If any of these bytes must be written, all three must be written before a reset is is

75、sued.</p><p>　　There is a ninth byte which may be read with a Read Scratchpad [BEH] command. This byte contains a cyclic redundancy check (CRC) byte which is the CRC over all of the eight previous bytes. Thi

76、s CRC is implemented in the fashion described in the section titled “CRC Generation”.</p><p>　　7 READ/WRITE TIME SLOTS</p><p>　　7.1 Write Time Slots</p><p>　　A write time slot is in

77、itiated when the host pulls the data line from a high logic level to a low logic level. There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots must be a minimum of 60 us

78、in duration with a minimum of a 1-μs recovery time between individual write cycles.</p><p>　　The DS18B20 samples the DQ line in a window of 15 us to 60 us after the DQ line falls. If the line is high, a Writ

79、e 1 occurs. If the line is low, a Write 0 occurs.</p><p>　　For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then released, allowing the data line to pull up

80、 to a high level within 15 us after the start of the write time slot. For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain low for 60us.</p><p>　　7.2 Rea

81、d Time Slots</p><p>　　The host generates read time slots when data is to be read from the DS18B20. A read time slot is initiated when the host pulls the data line from a logic high level to logic low level.

82、The data line must remain at a low logic level for a minimum of 1 us; output data from the DS18B20 is valid for 15 us after the falling edge of the read time slot. The host therefore must stop driving the DQ pin low in o