外文翻譯---具有8kb 系統(tǒng)可編程 flash 的8位微控制器

1、<p><b>　　附錄A</b></p><p><b>　　ATmega8</b></p><p>　　The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are dir

2、ectly connected to the Arithmetic Logic Unit (ALU),allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle.The resulting architecture is more code efficient while achieving t

3、hroughputs up toten times faster than conventional CISC microcontrollers.</p><p>　　The ATmega8 provides the following features:8K bytes of In-System Programmable Flash with Read-While-Write capabilities,512

4、bytes of EEPROM,1K byte of SRAM,23general purpose I/O lines,32 general purpose working registers, three flexibleTimer/Counters with compare modes, internal and external interrupts, a serial programmableUSART, a byte orie

5、nted Two-wire Serial Interface, a 6-channel ADC (eightchannels in TQFP and MLF packages) where four (six) channels have 10-bit accuracyand two channels have</p><p>　　The device is manufactured using Atmel’s

6、high density non-volatile memory technology.The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running

7、on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is

8、updated, providing </p><p>　　The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators

9、, and evaluation kits.</p><p>　　The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All inter

10、rupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.Depending on the Program Counter value, inte

11、rrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature impr</p><p>　　When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts ar

12、e disabled. The user software can write logic one to the I-bit to enable nested interrupts.All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interr

13、upt instruction – RETI – is executed.</p><p>　　There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is

14、vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit

15、 position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the</p><p>　　The second type of interrupts will trigger as long as the interrupt condition

16、 is present.These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.</p><p>　　When the AVR exits f

17、rom an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.Note that the Status Register is not automatically stored when entering an interrupt rou

18、tine,nor restored when returning from an interrupt routine. This must be handled by software.</p><p>　　When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No in

19、terrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.&

20、lt;/p><p>　　The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is exe

21、cuted. During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during executi

22、on of a multi-cycle instruction, this instruction is completed before the interrup</p><p>　　The ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR inst

23、ructions are 16- or 32-bits wide, the Flash is organized as 4K x 16 bits. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.</p>

24、;<p>　　The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory,and the next 1024 locations addres

25、s the internal data SRAM.The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, r

26、egisters R26 to R31 feature the indirect addressing pointer registers.The </p><p>　　The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can b

27、e read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described bellow, specifying the EEPROM Address Registers, the EEPROM Data Register, an

28、d the EEPROM Control Register.“Memory Programming” on page 219 contains a detailed description on EEPROM Programmingin SPI- or Parallel Programming mode.</p><p>　　All ATmega8 I/Os and peripherals are placed

29、in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 -0x1F are

30、 directly bit-accessible using the SBI and CBI instructions. In these registers,the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When

31、 using the I/O s</p><p>　　The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some extern

32、al interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clkI/O is

33、 halted, enabling TWI address reception in all sleep modes.</p><p>　　XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as

34、 shown in Figure 11. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a f

35、ull rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a </p><p><b>　　附錄B</b></p><p>　　具有8KB 系統(tǒng)可編

36、程 Flash 的8位微控制器</p><p>　　AVR 內(nèi)核具有豐富的指令集和32 個通用工作寄存器。所有的寄存器都直接與算邏單元(ALU) 相連接，使得一條指令可以在一個時鐘周期內(nèi)同時訪問兩個獨立的寄存器。這種結(jié)構(gòu)大大提高了代碼效率，并且具有比普通的CISC 微控制器最高至10 倍的數(shù)據(jù)吞吐率。</p><p>　　ATmega8 有如下特點：8K 字節(jié)的系統(tǒng)內(nèi)可編程Flash( 具

37、有同時讀寫的能力，即RWW)，512 字節(jié) EEPROM，1K 字節(jié) SRAM，32 個通用I/O 口線，32 個通用工作寄存器，三個具有比較模式的靈活的定時器/ 計數(shù)器(T/C), 片內(nèi)/ 外中斷，可編程串行USART，面向字節(jié)的兩線串行接口， 10 位6 路 (8 路為TQFP 與MLF 封裝)ADC，具有片內(nèi)振蕩器可編程看門狗定時器，一個SPI 串端口，以及五種可以通過軟件進行選擇的省電模式。工作于空閑模式時CPU 停止工作，而S

38、RAM、T/C、 SPI 端口以及中斷系統(tǒng)繼續(xù)工作；掉電模式時晶體振蕩器停止振蕩，所有功能除了中斷和硬件復位之外都停止工作；在省電模式下，異步定時器繼續(xù)運行，允許用戶保持一個時間基準，而其余功能模塊處于休眠狀態(tài)； ADC 噪聲抑制模式時終止CPU 和除了異步定時器與ADC 以外所有I/O 模塊的工作，以降低ADC 轉(zhuǎn)換時的開關噪聲； Standby 模式下只有晶體或諧振振蕩器運行，其余功能模塊處于休眠狀態(tài)，使得器件只消耗極少的電流，同時

39、具有快速啟動能力。</p><p>　　本芯片是以Atmel 高密度非易失性存儲器技術(shù)生產(chǎn)的。片內(nèi)ISP Flash 允許程序存儲器通過ISP 串行接口，或者通用編程器進行編程，也可以通過運行于AVR 內(nèi)核之中的引導程序進行編程。引導程序可以使用任意接口將應用程序下載到應用Flash存儲區(qū)(Application Flash Memory)。在更新應用Flash存儲區(qū)時引導Flash區(qū)(Boot Flash Me

40、mory)的程序繼續(xù)運行，實現(xiàn)了RWW 操作。 通過將8 位RISC CPU 與系統(tǒng)內(nèi)可編程的Flash 集成在一個芯片內(nèi)，ATmega8 成為一個功能強大的單片機，為許多嵌入式控制應用提供了靈活而低成本的解決方案。</p><p>　　ATmega8 具有一整套的編程與系統(tǒng)開發(fā)工具，包括：C 語言編譯器、宏匯編、 程序調(diào)試器/ 軟件仿真器、仿真器及評估板。</p><p>　　AVR有不

41、同的中斷源。每個中斷和復位在程序空間都有獨立的中斷向量。所有的中斷事件都有自己的使能位。當使能位置位，且狀態(tài)寄存器的全局中斷使能位I 也置位時，中斷可以發(fā)生。根據(jù)程序計數(shù)器PC 的不同，在引導鎖定位BLB02 或BLB12 被編程的情況下，中斷可能被自動禁止。這個特性提高了軟件的安全性。</p><p>　　任一中斷發(fā)生時全局中斷使能位I 被清零，從而禁止了所有其他的中斷。用戶軟件可以在中斷程序里置位I 來實現(xiàn)中

42、斷嵌套。此時所有的中斷都可以中斷當前的中斷服務程序。執(zhí)行RETI 指令后I 自動置位。</p><p>　　從根本上說有兩種類型的中斷。第一種由事件觸發(fā)并置位中斷標志。對于這些中斷，程序計數(shù)器跳轉(zhuǎn)到實際的中斷向量以執(zhí)行中斷處理程序，同時硬件將清除相應的中斷標志。中斷標志也可以通過對其寫的方式來清除。當中斷發(fā)生后，如果相應的中斷使能位為“0”，則中斷標志位置位，并一直保持到中斷執(zhí)行，或者被軟件清除。類似的，如果全局

43、中斷標志被清零，則所有已發(fā)生的中斷都不會被執(zhí)行，直到I 置位。然后掛起的各個中斷按中斷優(yōu)先級依次執(zhí)行。</p><p>　　第二種類型的中斷則是只要中斷條件滿足，就會一直觸發(fā)。這些中斷不需要中斷標志。若中斷條件在中斷使能之前就消失了，中斷不會被觸發(fā)。AVR 退出中斷后總是回到主程序并至少執(zhí)行一條指令才可以去執(zhí)行其他被掛起的中斷。</p><p>　　要注意的是，進入中斷服務程序時狀態(tài)寄存器

44、不會自動保存，中斷返回時也不會自動恢復。這些工作必須由用戶通過軟件來完成。使用CLI 指令來禁止中斷時，中斷禁止立即生效。沒有中斷可以在執(zhí)行CLI 指令后發(fā)生，即使它是在執(zhí)行CLI 指令的同時發(fā)生的。下面的例子說明了如何在寫EEPROM 時使用這個指令來防止中斷發(fā)生以避免對EEPROM 內(nèi)容的破壞。</p><p>　　AVR 中斷響應時間最少為4 個時鐘周期。4 個時鐘周期后，程序跳轉(zhuǎn)到實際的中斷處理例程。在這

45、4 個時鐘期期間PC 自動入棧。在通常情況下，中斷向量為一個跳轉(zhuǎn)指令，此跳轉(zhuǎn)需要3 個時鐘周期。如果中斷在一個多時鐘周期指令執(zhí)行期間發(fā)生，則在此多周期指令執(zhí)行完畢后MCU 才會執(zhí)行中斷程序。若中斷發(fā)生時MCU 處于休眠模式，中斷響應時間還需增加4 個時鐘周期。此外還要考慮到不同的休眠模式所需要的啟動時間。中斷返回需要4 個時鐘。在此期間PC( 兩個字節(jié)) 將被彈出棧，堆棧指針加二，狀態(tài)寄存器SREG 的I 置位。</p>

46、<p>　　ATmega8具有8K字節(jié)的在線編程Flash，用于存放程序指令代碼。因為所有的AVR指令為16位或32位，故而Flash組織成4K x 16位的形式。用戶程序的安全性要根據(jù)Flash程序存儲器的兩個區(qū)：引導(Boot) 程序區(qū)和應用程序區(qū)，分開來考慮。</p><p>　　Figure 8 給出了ATmega8 SRAM 空間的組織結(jié)構(gòu)。前1120 個數(shù)據(jù)存儲器包括了寄存器文件、I/O 存

47、儲器及內(nèi)部數(shù)據(jù)SRAM。起始的96 個地址為寄存器文件與I/O 存儲器，接著是1024 字節(jié)的內(nèi)部數(shù)據(jù)SRAM。數(shù)據(jù)存儲器的尋址方式分為5 種：直接尋址、帶偏移量的間接尋址、間接尋址、帶預減量的間接尋址和帶后增量的間接尋址。寄存器文件中的寄存器R26 到R31 為間接尋址的指針寄存器。直接尋址范圍可達整個數(shù)據(jù)區(qū)。帶偏移量的間接尋址模式能夠?qū)ぶ返接杉拇嫫鱕 和 Z 給定的基址附近的63 個地址。在自動預減和后加的間接尋址模式中，寄存器X、

48、Y 和Z 自動增加或減少。ATmega8的全部32個通用寄存器、64個I/O寄存器及1024個字節(jié)的內(nèi)部數(shù)據(jù)SRAM可以通過所有上述的尋址模式進行訪問。</p><p>　　ATmega8 包含512 字節(jié)的EEPROM 數(shù)據(jù)存儲器。它是作為一個獨立的數(shù)據(jù)空間而存在的，可以按字節(jié)讀寫。EEPROM 的壽命至少為100000 次擦除周期。EEPROM 的訪問由地址寄存器、數(shù)據(jù)寄存器和控制寄存器決定。P 209“存儲

49、器編程”包含使用SPI 或并行編程模式對EEPROM 編程。</p><p>　　ATmega8所有的I/O及外設都被放置于I/O空間。所有的I/O位置都可以通過IN 與OUT指令來訪問，在32 個通用工作寄存器和I/O 之間傳輸數(shù)據(jù)。 地址為0x00～0x1F 的I/O 寄存器還可用SBI 和CBI 指令直接進行位尋址，而SBIS 和SBIC 則用來檢查某一位的值。使用IN 和OUT指令時地址必須在 0x00

50、- 0x3F之間。如果要象SRAM樣通過LD 和ST 指令訪問I/O 寄存器，相應的地址要加上0x20。</p><p>　　I/O時鐘用于主要的I/O 模塊，如定時器/ 計數(shù)器、SPI 和USART。I/O 時鐘還用于外部中斷模塊。要注意的是有些外部中斷由異步邏輯檢測，因此即使I/O 時鐘停止了這些中斷仍然可以得到監(jiān)控。此外， USI 模塊的起始條件檢測在沒有clk的情況下也是異步實現(xiàn)的，使得這個功能在任何睡眠

51、模式下都可以正常工作。</p><p>　　XTAL1 與XTAL2 分別為用作片內(nèi)振蕩器的反向放大器的輸入和輸出，如Figure 11 所示，這個振蕩器可以使用石英晶體，也可以使用陶瓷諧振器。熔絲位CKOPT 用來選擇這兩種放大器模式的其中之一。當CKOPT 被編程時振蕩器在輸出引腳產(chǎn)生滿幅度的振蕩。這種模式適合于噪聲環(huán)境，以及需要通過XTAL2 驅(qū)動第二個時鐘緩沖器的情況。而且這種模式的頻率范圍比較寬。當保持