外文翻譯資料---電子時鐘設(shè)計(jì)

1、<p><b>　　中文2722字</b></p><p><b>　　外文資料翻譯</b></p><p>　　LED using digital tube digital display its high-brightness, indicating the advantages of intuitive intelligence

2、is widely used in areas such as equipment and household appliances. AT89C52This article describes a single-chip microcomputer as the core, to a total of anode high-brightness LED L ED as a display composed of seven figur

3、es show that the practical design of multi-function electronic clocks, the clock shows a week, hour, minute, second, it can be switched to year, month, day showed that </p><p>　　Clock circuit is the heart of

4、 the computer, which controls the rhythm of the work of the computer is through the completion of complex sequential circuits function in different directions.</p><p>　　Clock, since it was invented that day

5、on, people's lives has become an indispensable tool, especially in this era of efficient, the clock is in the human production and living, learning and other fields is widely. However, with the passage of time, peopl

6、e not only to the requirements of the clock is getting higher and higher precision, and functional requirements for the clock more and more, the clock has not only a tool used to display time, in many practical applicati

7、ons It also needs to be ab</p><p>　　With the development of human civilization, science and technology, there is the request of the clock continues to improve. Clock has not only seen as a tool to display th

8、e time, in many practical applications also need to be able to achieve more other functions. High-precision, multifunction, small size, low power consumption, is the development trend of the modern clock. In this trend,

9、digital clock, multifunction clock has become the modern design of the production of research-led direction. </p><p>　　The design is based on the principle of single-chip technology to chip AT89C52single-chi

10、p microcomputer as the core controller, through the production of hardware and software procedures for the preparation, design to produce a multi-functional digital clock system. The clock system mainly by clock module,

11、alarm module, the ambient temperature detection module, liquid crystal display module, control module and the keyboard signal prompted module. System is simple and clear user interface that ca</p><p>　　Clock

12、 design is no theory of discrete logic, programmable logic, or using full-custom silicon devices of any digital design, in order to successfully operate and reliable clock is crucial. Poor design of the clock in the limi

13、ts of temperature, voltage deviation or the manufacturing process will result in the case wrong, and debugging difficult, spending a lot. In the design of FPGA / CPLD clock when several types of commonly used. Clock can

14、be divided into the following four types: global clock,</p><p>　　No matter what methods are the real circuit clock tree can not achieve the ideal assumption that the clock, so we must be based on an ideal cl

15、ock, the clock real work to build a model to analyze the circuit, so as to make the circuit performance and the practical work as expected . Clock in the actual model, we have to consider the spread of clock-tree skew, v

16、ertical jump and absolute bias and other uncertainties. </p><p>　　To register, the clock was working along the arrival of the data terminal when it should have been stable, so as to ensure that the work alon

17、g the sampling clock to the accuracy of the data, this data preparation time that we call set-up time (setup time). Data should also be working along the clock to maintain over a period of time, this period of time known

18、 as the hold time (hold time). </p><p>　　Global clock for a design project, the global clock (or clock synchronous) is the simplest and most predictable clock. In the PLD / FPGA design of the clock the best

19、options are: by a dedicated global clock input pins of a single master clock-driven clock design projects to each flip-flop. As long as possible should be used in the design of global clock projects. PLD / FPGA has a ded

20、icated global clock pins, the device is directly connected to each register. Global clock to provide such a device</p><p>　　Clock-gated in many applications, the entire design of the overall use of external

21、clock is not possible or practical. With the product of PLD logic array clock (that is, the clock is generated by the logic), to allow arbitrary function alone all trigger clock. However, when you use the array clock, th

22、e clock should be carefully analyzed the function, in order to avoid glitches. </p><p>　　Usually constitute the array clock clock-gated. Clock gating often interface with the microprocessor, and used the add

23、ress to write to control the pulse line. However, when using combination of flip-flop when the clock function, usually there is a clock-gated. If the following conditions, such as clock gating can be as reliable as globa

24、l clock work: </p><p>　　Drive the clock logic must contain only one "and" the door or a "or" gate. If any additional work in some state of logic, the competition will be the burr. </p&

25、gt;<p>　　A logic gate input as the actual clock, and the logic gate must be of all other input as the address or control lines, in relation to their compliance with the establishment and maintenance of clock time

26、bound. </p><p>　　Multi-level logic generated clock when the clock-gating logic of the combination of more than one (or more than the individual "and" doors or "or" gate), the evidence of

27、the reliability of the design of the project has become very difficult. Even if the prototype or simulation results show that there is no static dangerous, but in fact the risk may still exist. In general, we should not

28、use multi-level combinational logic to clock the flip-flop in the PLD design. </p><p>　　Traveling-wave clock clock another popular use of traveling-wave circuit is the clock, that is, the output of a flip-fl

29、op used as a clock input of another flip-flop. If careful design, traveling-wave clock can be the same as the global clock to work reliably. However, the traveling-wave clock made from time to time with the calculation o

30、f the circuit becomes very complicated. Line-wave traveling-wave clock flip-flop of the chain have a greater clock time between the offset and exceed the worst c</p><p>　　Multi-clock system, many system requ

31、irements within the same multi-PLD clock. The most common example is the two asynchronous interfaces between microprocessors, or microprocessors and asynchronous communication channel interface. As the clock signal betwe

32、en the two requirements to establish and maintain a certain time, so that the above application from time to time the introduction of additional constraints. They also requested that some asynchronous synchronization sig

33、nal. </p><p>　　In many applications, only the synchronization of asynchronous signals is not enough, when the system of two or more non-homologous clock, the data it is difficult to establish and maintain th

34、e time to be assured that we will face the complex matter of time . The best way is to all non-homologous clock synchronization. PLD internal use of the lock loop (PLL or DLL) is a very good, but not all of PLD with a PL

35、L, DLL, and chip PLL with most expensive, so unless there are special requirements, the </p><p>　　采用L ED 數(shù)碼管的數(shù)字顯示以其亮度高、顯示直觀等優(yōu)點(diǎn)被廣泛應(yīng)用于智能儀器及家用電器等領(lǐng)域. 本文介紹一種以AT89C52單片機(jī)為核心,以共陽極高亮度L ED 數(shù)碼管作為顯示器件組成7 位數(shù)字顯示的實(shí)用多功能電子時鐘

36、的設(shè)計(jì),該時鐘可顯示星期、時、分、秒,也可切換為年、月、日顯示,同時具有整點(diǎn)音樂報時及定時鬧鐘等功能,也可作電子秒表使用。</p><p>　　時鐘電路是計(jì)算機(jī)的心臟, 它控制著計(jì)算機(jī)的工作節(jié)奏就是通過復(fù)雜的時序電路完成不同的指令功能的。</p><p>　　時鐘，自從它被發(fā)明的那天起，就成為人們生活中必不可少的一種工具，尤其是在現(xiàn)在這個講究效率的年代，時鐘更是在人類生產(chǎn)、生活、學(xué)習(xí)等多個

37、領(lǐng)域得到廣泛的應(yīng)用。然而隨著時間的推移，人們不僅對于時鐘精度的要求越來越高，而且對于時鐘功能的要求也越來越多，時鐘已不僅僅是一種用來顯示時間的工具，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。諸如鬧鐘功能、日歷顯示功能、溫度測量功能、濕度測量功能、電壓測量功能、頻率測量功能、過欠壓報警功能等。鐘表的數(shù)字化給人們的生產(chǎn)生活帶來了極大的方便，而且大大地擴(kuò)展了鐘表原先的報時功能。諸如定時自動報警、按時自動打鈴、時間程序自動控制、定時廣播、

38、自動起閉路燈、定時開關(guān)烘箱、通斷動力設(shè)備、甚至各種定時電氣的自動啟用等，所有這些，都是以鐘表數(shù)字化為基礎(chǔ)的?？梢哉f，設(shè)計(jì)多功能數(shù)字時鐘的意義已不只在于數(shù)字時鐘本身，更大的意義在于多功能數(shù)字時鐘在許多實(shí)時控制系統(tǒng)中的應(yīng)用。在很多實(shí)際應(yīng)用中，只要對數(shù)字時鐘的程序和硬件電路加以一定的修改，便可以得到實(shí)時控制的實(shí)用系統(tǒng)，從而應(yīng)用到實(shí)際工作與生產(chǎn)中去。因此，研究數(shù)字時鐘及擴(kuò)大其應(yīng)用，有著非?，F(xiàn)實(shí)的意義。</p><p>　

39、　隨著人類科技文明的發(fā)展，人們對于時鐘的要求在不斷地提高。時鐘已不僅僅被看成一種用來顯示時間的工具，在很多實(shí)際應(yīng)用中它還需要能夠?qū)崿F(xiàn)更多其它的功能。高精度、多功能、小體積、低功耗，是現(xiàn)代時鐘發(fā)展的趨勢。在這種趨勢下，時鐘的數(shù)字化、多功能化已經(jīng)成為現(xiàn)代時鐘生產(chǎn)研究的主導(dǎo)設(shè)計(jì)方向。本文正是基于這種設(shè)計(jì)方向，以單片機(jī)為控制核心，設(shè)計(jì)制作一個符合指標(biāo)要求的多功能數(shù)字時鐘。</p><p>　　本設(shè)計(jì)基于單片機(jī)技術(shù)原理，以

40、單片機(jī)芯片AT89C52作為核心控制器，通過硬件電路的制作以及軟件程序的編制，設(shè)計(jì)制作出一個多功能數(shù)字時鐘系統(tǒng)。該時鐘系統(tǒng)主要由時鐘模塊、鬧鐘模塊、環(huán)境溫度檢測模塊、液晶顯示模塊、鍵盤控制模塊以及信號提示模塊組成。系統(tǒng)具有簡單清晰的操作界面，能在4V～7V直流電源下正常工作。能夠準(zhǔn)確顯示時間（顯示格式為時時：分分：秒秒，24小時制），可隨時進(jìn)行時間調(diào)整，具有鬧鐘時間設(shè)置、鬧鐘開/關(guān)、止鬧功能，能夠?qū)r鐘所在的環(huán)境溫度進(jìn)行測量并顯示。設(shè)計(jì)

41、以硬件軟件化為指導(dǎo)思想，充分發(fā)揮單片機(jī)功能，大部分功能通過軟件編程來實(shí)現(xiàn)，電路簡單明了，系統(tǒng)穩(wěn)定性高。同時，該時鐘系統(tǒng)還具有功耗小、成本低的特點(diǎn)，具有很強(qiáng)的實(shí)用性。由于系統(tǒng)所用元器件較少，單片機(jī)所被占用的I/O口不多，因此系統(tǒng)具有一定的可擴(kuò)展性。</p><p>　　時鐘設(shè)計(jì)無淪是用離散邏輯、可編程邏輯，還是用全定制硅器件實(shí)現(xiàn)的任何數(shù)字設(shè)計(jì)，為了成功地操作，可靠的時鐘是非常關(guān)鍵的。設(shè)計(jì)不良的時鐘在極限的溫度、電壓

42、或制造工藝的偏差情況下將導(dǎo)致錯誤的行為，并且調(diào)試?yán)щy、花銷很大。在設(shè)計(jì)FPGA/CPLD時通常采用幾種時鐘類型。時鐘可分為如下四種類型：全局時鐘、門控時鐘、多級邏輯時鐘和波動式時鐘。多時鐘系統(tǒng)能夠包括上述四種時鐘類型的任意組合。</p><p>　　無論采用何種方式，電路中真實(shí)的時鐘樹也無法達(dá)到假定的理想時鐘，因此我們必須依據(jù)理想時鐘，建立一個實(shí)際工作時鐘模型來分析電路，這樣才可以使得電路的實(shí)際工作效果和預(yù)期的一

43、樣。在實(shí)際的時鐘模型中，我們要考慮時鐘樹傳播中的偏斜、跳變和絕對垂直的偏差以及其它一些不確定因素。</p><p>　　對于寄存器而言，當(dāng)時鐘工作沿到來時它的數(shù)據(jù)端應(yīng)該已經(jīng)穩(wěn)定，這樣才能保證時鐘工作沿采樣到數(shù)據(jù)的正確性，這段數(shù)據(jù)的預(yù)備時間我們稱之為建立時間（setup time）。數(shù)據(jù)同樣應(yīng)該在時鐘工作沿過去后保持一段時間，這段時間稱為保持時間（hold time）。</p><p>　　

44、全局時鐘對于一個設(shè)計(jì)項(xiàng)目來說，全局時鐘(或同步時鐘)是最簡單和最可預(yù)測的時鐘。在PLD/FPGA設(shè)計(jì)中最好的時鐘方案是：由專用的全局時鐘輸入引腳驅(qū)動的單個主時鐘去鐘控設(shè)計(jì)項(xiàng)目中的每一個觸發(fā)器。只要可能就應(yīng)盡量在設(shè)計(jì)項(xiàng)目中采用全局時鐘。PLD/FPGA都具有專門的全局時鐘引腳，它直接連到器件中的每一個寄存器。這種全局時鐘提供器件中最短的時鐘到輸出的延時。</p><p>　　門控時鐘在許多應(yīng)用中，整個設(shè)計(jì)項(xiàng)目都采用

45、外部的全局時鐘是不可能或不實(shí)際的。PLD具有乘積項(xiàng)邏輯陣列時鐘（即時鐘是由邏輯產(chǎn)生的），允許任意函數(shù)單獨(dú)地鐘控各個觸發(fā)器。然而，當(dāng)你用陣列時鐘時，應(yīng)仔細(xì)地分析時鐘函數(shù)，以避免毛刺。</p><p>　　通常用陣列時鐘構(gòu)成門控時鐘。門控時鐘常常同微處理器接口有關(guān)，用地址線去控制寫脈沖。然而，每當(dāng)用組合函數(shù)鐘控觸發(fā)器時，通常都存在著門控時鐘。如果符合下述條件，門控時鐘可以象全局時鐘一樣可靠地工作：</p>

46、<p>　　驅(qū)動時鐘的邏輯必須只包含一個“與”門或一個“或”門。如果采用任何附加邏在某些工作狀態(tài)下，會出現(xiàn)競爭產(chǎn)生的毛刺。</p><p>　　邏輯門的一個輸入作為實(shí)際的時鐘，而該邏輯門的所有其它輸入必須當(dāng)成地址或控制線，它們遵守相對于時鐘的建立和保持時間的約束。</p><p>　　多級邏輯時鐘當(dāng)產(chǎn)生門控時鐘的組合邏輯超過一級(即超過單個的“與”門或“或”門)時，證設(shè)計(jì)項(xiàng)目

47、的可靠性變得很困難。即使樣機(jī)或仿真結(jié)果沒有顯示出靜態(tài)險象，但實(shí)際上仍然可能存在著危險。通常，我們不應(yīng)該用多級組合邏輯去鐘控PLD設(shè)計(jì)中的觸發(fā)器。</p><p>　　行波時鐘另一種流行的時鐘電路是采用行波時鐘，即一個觸發(fā)器的輸出用作另一個觸發(fā)器的時鐘輸入。如果仔細(xì)地設(shè)計(jì)，行波時鐘可以象全局時鐘一樣地可靠工作。然而，行波時鐘使得與電路有關(guān)的定時計(jì)算變得很復(fù)雜。行波時鐘在行波鏈上各觸發(fā)器的時鐘之間產(chǎn)生較大的時間偏移，

48、并且會超出最壞情況下的建立時間、保持時間和電路中時鐘到輸出的延時，使系統(tǒng)的實(shí)際速度下降。</p><p>　　多時鐘系統(tǒng)許多系統(tǒng)要求在同一個PLD內(nèi)采用多時鐘。最常見的例子是兩個異步微處理器器之間的接口，或微處理器和異步通信通道的接口。由于兩個時鐘信號之間要求一定的建立和保持時間，所以，上述應(yīng)用引進(jìn)了附加的定時約束條件。它們也會要求將某些異步信號同步化。</p><p>　　在許多應(yīng)用中只

49、將異步信號同步化還是不夠的，當(dāng)系統(tǒng)中有兩個或兩個以上非同源時鐘的時候，數(shù)據(jù)的建立和保持時間很難得到保證，我們將面臨復(fù)雜的時間問題。最好的方法是將所有非同源時鐘同步化。使用PLD內(nèi)部的鎖項(xiàng)環(huán)（PLL或DLL）是一個效果很好的方法，但不是所有PLD都帶有PLL、DLL，而且?guī)в蠵LL功能的芯片大多價格昂貴，所以除非有特殊要求，一般場合可以不使用帶PLL的PLD。這時我們需要使用帶使能端的D觸發(fā)器，并引入一個高頻時鐘。</p>