有關(guān)a d（模數(shù))轉(zhuǎn)換的外文翻譯

1、<p>　　ICL7135 4 1/2 Digit, BCD Output, A/D Converter</p><p>　　The Intersil ICL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, combines dual-slope conversion reliability

2、with +1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The 2.0000V full scale capability, auto-zero, and auto-polarity are combined with true ratiometric operation, almost ideal dif

3、ferential linearity and true differential input. All necessary active devices are contained on a single CMOS lC, with the exception of displ</p><p>　　The ICL7135 brings together an unprecedented combination

4、of high accuracy, versatility, and true economy. It features auto-zero to less than 10µ V, zero drift of less than 1µV/℃, input bias current of 10pA (Max), and rollover error of less than one count. The versati

5、lity of multiplexed BCD outputs is increased by the addition of several pins which allow it to operate in more sophisticated systems. These include STROBE , OVERRANGE , UNDERRANGE , RUN/HOLD and BUSY lines, making it p

6、ossible to in</p><p><b>　　Features</b></p><p>　　* Accuracy Guaranteed to+1 Count Over Entire 20000 Counts (2.0000V Full Scale)</p><p>　　* Guaranteed Zero Reading for 0V

7、Input</p><p>　　* 1pA Typical Input Leakage Current</p><p>　　* True Differential Input</p><p>　　* True Polarity at Zero Count for Precise Null Detection</p><p>　　* Singl

8、e Reference Voltage Required</p><p>　　* Over range and Under range Signals Available for Auto-Range Capability</p><p>　　* All Outputs TTL Compatible</p><p>　　* Blinking Outputs Give

9、s Visual Indication of Over range</p><p>　　* Six Auxiliary Inputs/Outputs are Available for Interfacing to UARTs , Microprocessors, or Other Circuitry</p><p>　　* Multiplexed BCD Outputs</p&

10、gt;<p>　　* Pb-Free Available (RoHS Compliant)</p><p>　　Detailed Description</p><p>　　Analog Section</p><p>　　Each measurement cycle is divided into four phases. They are (1)

11、auto-zero (AZ), (2) signal-integrate (INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).</p><p>　　Auto-Zero Phase</p><p>　　During auto-zero, three things happen. First, input high and low

12、 are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero cap

13、acitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case,<

14、/p><p>　　Signal Integrate Phase</p><p>　　During signal integrate , the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pin

15、s. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range; within one volt of either supply. If, on the other han

16、d, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establis</p><p>　　De-Integrate Phase</p><p>　　The third phase is de-integrate

17、or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor wil

18、l be connected with the correct polarity to cause the integrator output to return to zero. The time required for the out- put to return to zero is proportional to the input signal. Specifically the digital read

19、ing displayed is:</p><p>　　Zero Integrator Phase</p><p>　　The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed around the system to

20、 input high to cause the integrator output to return to zero. Under normal condition, this phase lasts from 100 to 200 clock pulses, but after an over range conversion, it is extended to 6200 clock pulses.</p><

21、;p>　　Differential Input</p><p>　　The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 0.5V below the positive supply to 1V above th

22、e negative supply. In this range the system has a CMRR of 86dB typical. However, since the integrator also swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A

23、worst case condition would be a large positive common-mode voltage with a near full scale negative differenti</p><p>　　Analog COMMON</p><p>　　Analog COMMON is used as the input low return during

24、 auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in most applications IN LO will be s

25、et at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The reference voltage is refe

26、renced t</p><p><b>　　Reference</b></p><p>　　The reference input must be generated as a positive voltage with respect to COMMON,</p><p>　　Digital Section</p><p

27、>　　Figure 5 shows the Digital Section of the ICL7135. The ICL7135 includes several pins which allow it to operate conveniently in more sophisticated systems. These include:</p><p>　　Run/HOLD (Pin 25)</

28、p><p>　　When high (or open) the A/D will free-run with equally spaced measurement cycles every 40,002 clock pulses. If taken low, the converter will continue the full measurement cycle that it is doing and then

29、 hold this reading as long as R/H is held low. A short positive pulse (greater than 300ns) will now initiate a new measurement cycle, beginning with between 1 and 10,001 counts of auto zero. If the pulse occurs before th

30、e full measurement cycle (40,002 counts) is completed, it will not be recogniz</p><p>　　STROBE (Pin 26)</p><p>　　This is a negative going output pulse that aids in transferring the BCD data to e

31、xternal latches, UARTs, or microprocessors. There are 5 negative going STROBE pulses that occur in the center of each of the digit drive pulses and occur once and only once for each measurement cycle starting 101 clock p

32、ulses after the end of the full measurement cycle. Digit 5 (MSD) goes high at the end of the measurement cycle and stays on for 201 counts. In the center of this digit pulse (to avoid race conditions</p><p>

33、　　BUSY (Pin 21)</p><p>　　BUSY goes high at the beginning of signal integrate and stays high until the first clock pulse after zero crossing (or after end of measurement in the case of an over range). The int

34、ernal latches are enabled (i.e., loaded) during the first clock pulse after busy and are latched at the end of this clock pulse. The circuit automatically reverts to auto-zero when not BUSY, so it may also be considered

35、a (Zl + AZ) signal. A very simple means for transmitting the data down a single wire pair from a r</p><p>　　OVERRANGE (Pin 27)</p><p>　　This pin goes positive when the input signal exceeds the r

36、ange (20,000) of the converter. The output F/F is set at the end of BUSY and is reset to zero at the beginning of reference integrate in the next measurement cycle.</p><p>　　UNDERRANGE (Pin 28)</p>&l

37、t;p>　　This pin goes positive when the reading is 9% of range or less. The output F/F is set at the end of BUSY (if the new reading is 1800 or less) and is reset at the beginning of signal integrate of the next reading

38、.</p><p>　　POLARlTY (Pin 23)</p><p>　　This pin is positive for a positive input signal. It is valid even for a zero reading. In other words, +0000 means the signal is positive but less than the

39、least significant bit. The converter can be used as a null detector by forcing equal frequency of (+) and (-) readings. The null at this point should be less than 0.1 LSB. This output becomes valid at the beginning of re

40、ference integrate and remains correct until it is revalidated for the next measurement.</p><p>　　Digit Drives (Pins 12, 17, 18, 19 and 20)</p><p>　　Each digit drive is a positive going signal th

41、at lasts for 200 clock pulses. The scan sequence is D5 (MSD), D4 , D3 , D2 , and D1 (LSD). All five digits are scanned and this scan is continuous unless an over range occurs. Then all digit drives are blanked from the e

42、nd of the strobe sequence until the beginning of Reference Integrate when D5 will start the scan again. This can give a blinking display as a visual indication of over range.</p><p>　　BCD (Pins 13, 14, 15 an

43、d 16)</p><p>　　The Binary coded Decimal bits B8 , B4 , B2 , and B1 are positive logic signals that go on simultaneously with the digit driver signal.</p><p>　　Component Value Selection</p>

44、<p>　　For optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These valu

45、es must be chosen to suit the particular application.</p><p>　　Integrating Resistor</p><p>　　The integrating resistor is determined by the full scale input voltage and the output current of the

46、buffer used to charge the integrator capacitor. Both the buffer amplifier and the integrator have a class A output stage with 100 µA of quiescent current. They can supply 20µ A of drive current with negligible

47、non-linearity. Values of 5µ A to 40 µA give good results, with a nominal of 20 µA, and the exact value of integrating resistor may be chosen by:</p><p>　　Integrating Capacitor</p><p

48、>　　The product of integrating resistor and capacitor should be selected to give the maximum voltage swing which ensures that the tolerance built-up will not saturate the integrator swing (approx. 0.3V from either supp

49、ly). For +5V supplies and analog COMMON tied to supply ground, a +3.5V to +4V full scale integrator swing is fine, and 0.47µ F is nominal. In general, the value of CINT is given by:</p><p>　　A very impo

50、rtant characteristic of the integrating capacitor is that it has low dielectric absorption to prevent roll-over or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to

51、the reference.</p><p>　　This ratiometric condition should read half scale 0.9999, and any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable c

52、ost. Polystyrene and polycarbonate capacitors may also be used in less critical applications.</p><p>　　Auto-Zero and Reference Capacitor</p><p>　　The physical size of the auto-zero capacitor has

53、 an influence on the noise of the system. A larger capacitor value reduces system noise. A larger physical size increases system noise. The reference capacitor should be large enough such that stray capacitance to ground

54、 from its nodes is negligible .</p><p>　　The dielectric absorption of the reference cap and auto-zero cap are only important at power-on or when the circuit is recovering from an overload. Thus, smaller or c

55、heaper caps can be used here if accurate readings are not required for the first few seconds of recovery.</p><p>　　Reference Voltage</p><p>　　The analog input required to generate a full scale o

56、utput is </p><p>　　The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high quality reference be used where h

57、igh-accuracy absolute measurements are being made.</p><p>　　Rollover Resistor and Diode</p><p>　　A small rollover error occurs in the ICL7135, but this can be easily corrected by adding a diode

58、and resistor in series between the INTegrator OUTput and analog COMMON or ground. The value shown in the schematics is optimum for the recommended conditions, but if integrator swing or clock frequency is modified, adjus

59、tment may be needed. The diode can be any silicon diode such as 1N914. These components can be eliminated if rollover error is not important and may be altered in value to correct oth</p><p>　　Max Clock Freq

60、uency</p><p>　　The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3µs

61、 delay, and at a clock frequency of 160kHz (6µs period) half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2

62、with a 150 µV input, 2 to 3 with a 250µ V input, etc. This transition at mid-point is considered desira</p><p>　　For many dedicated applications where the input signal is always of one polarity, th

63、e delay of the comparator need not be a limitation. Since the non-linearity and noise do not increase substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count or

64、counts caused by comparator delay will be constant and can be subtracted out digitally.</p><p>　　The clock frequency may be extended above 160kHz without this error, however, by using a low value resistor in

65、 serieswith the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio

66、between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequenc</p><p>　　The minimum clock frequency

67、 is established by leakage on the auto-zero and reference caps. With most devices, measurement cycles as long as 10s give no measurable leakage error.</p><p>　　To achieve maximum rejection of 60Hz pickup, th

68、e signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz, 40kHz, 33 kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 250kHz, 166kH

69、z, 125kHz, 100kHz, etc. would be suitable. Note that 100kHz (2.5 readings/sec) will reject both 50Hz and 60Hz.</p><p>　　The clock used should be free from significant phase or frequency jitter. Several suita

70、ble low-cost oscillators are shown in the Typical Applications section. The multiplexed output means that if the display takes significant current from he logic supply, the clock should have good PSRR.</p><p&g

71、t;　　Zero-Crossing Flip-Flop</p><p>　　The flip-flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. False zero-crossings caus

72、ed by clock pulses are not recognized. Of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. There

73、fore, the counter is disabled for one clock pulse at the beginning of phase 3. This one-count delay compensate</p><p>　　Evaluating The Error Sources</p><p>　　Errors from the ”ideal” cycle are ca

74、used by:</p><p>　　1. Capacitor droop due to leakage.</p><p>　　2. Capacitor voltage change due to charge “suck-out” (the reverse of charge injection) when the switches turn off.</p><p&

75、gt;　　3. Non-linearity of buffer and integrator.</p><p>　　4. High-frequency limitations of buffer, integrator, and comparator.</p><p>　　5. Integrating capacitor non-linearity (dielectric absorpti

76、on).</p><p>　　6. Charge lost by in charging </p><p>　　7. Charge lost by and to charge </p><p>　　Each error is analyzed for its error contribution to the converter in application n

77、otes listed on the back page, specifically Application Note AN017 and Application Note AN032.</p><p><b>　　Noise</b></p><p>　　The peak-to-peak noise around zero is approximately 15

78、81; V (peak-to-peak value not exceeded 95% of the time). Near full scale, this value increases to approximately 30 µV. Much of the noise originates in the auto-zero loop, and is proportional to the ratio of the inpu

79、t signal to the reference.</p><p>　　Analog And Digital Grounds</p><p>　　Extreme care must be taken to avoid ground loops in the layout of ICL7135 circuits, especially in high-sensitivity circuit

80、s. It is most important that return currents from digital loads are not fed into the analog ground line.</p><p>　　Power Supplies</p><p>　　The ICL7135 is designed to work from +5V supplies. Howev

81、er, in selected applications no negative supply is required. The conditions to use a single +5V supply are:</p><p>　　1. The input signal can be referenced to the center of the common mode range of the conver

82、ter.</p><p>　　2. The signal is less than +1.5V.</p><p><b>　　外文資料譯文</b></p><p>　　ICL7135 4 1/2 Digit, BCD Output, A/D Converter</p><p>　　ICL7135是由INTERSIL公司

83、生產(chǎn)的高精度A/D轉(zhuǎn)換器， 它的雙斜率積分轉(zhuǎn)換可靠性可達(dá)到在20,000計(jì)數(shù)中有+1的誤差，另外加上它的數(shù)字軀動(dòng)輸出端以及多路復(fù)用的二一十進(jìn)制碼(BCD)輸出端，就可以應(yīng)用于數(shù)字電壓表，數(shù)字電流表的顯示。它的大部分電路都集中在CMOS工藝的集成芯片中，只要附加譯碼器，數(shù)碼顯示器，驅(qū)動(dòng)器及參考電壓和時(shí)鐘，就可組成一個(gè)滿量程為2V的數(shù)字電壓表，它具有自動(dòng)進(jìn)行調(diào)零操作，自動(dòng)極性轉(zhuǎn)換等功能。</p><p>　　ICL7

84、135具有高精確度， 通用性和經(jīng)濟(jì)等優(yōu)點(diǎn)。 零點(diǎn)誤差小于10µv. 零點(diǎn)漂移小于1 µV/℃.低輸入電流(小于10PA)使源阻抗誤差為最小。 翻轉(zhuǎn)誤差限制在士1計(jì)數(shù)值. BUSY, STROBE, RUN/BOLD, OVERRANGE以及UNDER RANGE控制信號(hào)支持基于微處理器的測(cè)量系統(tǒng)?？刂菩盘?hào)也能支持通過(guò)通用異步接收器發(fā)送器(UART )進(jìn)行數(shù)據(jù)傳送的遠(yuǎn)程數(shù)據(jù)采集系統(tǒng)。</p><p&

85、gt;<b>　　特點(diǎn)：</b></p><p>　　* 在20,000計(jì)數(shù)中有+1的誤差（2V滿量程）</p><p><b>　　* 0v輸入零讀數(shù)</b></p><p>　　* IPA典型輸入電流</p><p><b>　　* 真正差分輸入</b></p>

86、<p>　　* 需要的唯一參考電壓</p><p>　　* Over range和Under range信號(hào)的自動(dòng)范圍能力</p><p><b>　　* TTL兼容性</b></p><p>　　* 控制信號(hào)允許與UARTS或微處理器接口</p><p>　　* 多路復(fù)用二十進(jìn)制代碼(BCD)輸出<

87、/p><p><b>　　* 無(wú)鉛工藝</b></p><p><b>　　詳細(xì)描寫(xiě)</b></p><p><b>　　模擬部分</b></p><p>　　每個(gè)測(cè)量周期被劃分成四個(gè)階段。 他們是(1)自動(dòng)調(diào)零(AZ)， (2)信號(hào)積分(INT)， (3) 去積分(DE)和(4)

88、積分器返回零(Zl)。</p><p><b>　　自動(dòng)調(diào)零</b></p><p>　　在自動(dòng)調(diào)零階段，處理3件事。第一，自動(dòng)調(diào)零相.內(nèi)部IN+和IN-輸入與引腳斷開(kāi)且在內(nèi)部連接至模擬地。第二，基準(zhǔn)電容被充電至基準(zhǔn)電壓。第三，系統(tǒng)接成閉環(huán)。自動(dòng)調(diào)零電容被充電以補(bǔ)償緩沖放大器。積分器和比較器的失調(diào)電壓。自動(dòng)調(diào)零精度僅受系統(tǒng)噪聲的限制。以輸入為基準(zhǔn)的總失調(diào)小于10

89、81;V。</p><p><b>　　信號(hào)積分</b></p><p>　　在信號(hào)積分階段，自動(dòng)調(diào)零環(huán)路被打開(kāi)，內(nèi)部短路被移除。內(nèi)部的IN+和IN-輸入被連接至外部引腳。在固定的時(shí)間周期內(nèi)這些輸入端之間的差分電壓被積分。這些差分電壓可以工作在一個(gè)廣泛的共模范圍內(nèi)。如果，在另一方面，當(dāng)輸入信號(hào)相對(duì)于轉(zhuǎn)換器電源不反相時(shí)。IN-連接至模擬地以建立正確的共模電壓。在這一相完

90、成的基礎(chǔ)上。輸入信號(hào)的極性被記錄。</p><p><b>　　去積分</b></p><p>　　第三階段為去積分或參考積分階段，基準(zhǔn)用于完成去積分任務(wù)，內(nèi)部IN-在內(nèi)部連接至模擬地, IN+跨接至先前已充電的基準(zhǔn)電容。所記錄的輸入信號(hào)的極性確保以正確的極性連接電容以便積分器輸出極性回到零，輸出返回至零所需的時(shí)間正比于輸入信號(hào)的幅度，返回時(shí)間顯示為數(shù)宇讀數(shù)并由等式1

91、0000×（VIN/VREF）確定。滿度或最大轉(zhuǎn)換值發(fā)生在VID等于兩倍VREF時(shí)。</p><p><b>　　積分器返回零.</b></p><p>　　最后一個(gè)階段為積分返回零階段，第一，內(nèi)部的IN-連接到模擬地。第二，系統(tǒng)接成閉環(huán)以便使積分器輸出返回到零。通常這一相需要100至200個(gè)時(shí)鐘脈沖。但是在超范圍轉(zhuǎn)換后，需要6200個(gè)脈沖。</p&g

92、t;<p><b>　　輸入信號(hào)范圍</b></p><p>　　輸入信號(hào)可以接受任何的差分信號(hào)，只要輸入放大器的共模范圍從負(fù)電源電壓加1V延展到正電源電壓減0.5V。在此范圍內(nèi).共模抑制比（CMRR）的典型值為86dB。差分和共模電壓二者均使積分器的輸出擺動(dòng)。因此.必須小心確保積分器的輸出不變成飽和。最壞的情況是出現(xiàn)大量正的共模電壓與附近的負(fù)的差分輸入電壓。負(fù)的輸入信號(hào)積分到

93、達(dá)正時(shí)，其大部分的擺動(dòng)已消耗掉共模電壓。為這些重要應(yīng)用與一些精確損失，建議使用的4V全方位擺動(dòng)可以減少積分器擺動(dòng)。積分器輸出可能在任一輸入之內(nèi)達(dá)到0.3V擺動(dòng)，不會(huì)產(chǎn)生線性損失。</p><p><b>　　模擬公共端</b></p><p>　　在自動(dòng)調(diào)零.去積分以及積分器返零相期間內(nèi)，模擬公共端連接到內(nèi)部IN-。在信號(hào)積分相期間內(nèi)，IN-連接到與模擬公共端不同的電

94、壓.此時(shí)所產(chǎn)生的共模電壓被放大器抑制，但是.在大多數(shù)應(yīng)用中.IN-被置于已知的固定電壓(即，例如電源的公共端).在這種應(yīng)用中.模擬公共端應(yīng)當(dāng)連接到同樣的點(diǎn).于是從轉(zhuǎn)換器除去模電壓。用這種方式消除共模電壓可稍微提高轉(zhuǎn)換精度。</p><p><b>　　基準(zhǔn)</b></p><p>　　基準(zhǔn)電壓相對(duì)于模擬公共端為正。轉(zhuǎn)換結(jié)果的精度取決于基準(zhǔn)的質(zhì)量。因此.為了得到高精度的

95、轉(zhuǎn)換，應(yīng)當(dāng)使用高質(zhì)量的基準(zhǔn)</p><p><b>　　數(shù)字部分</b></p><p>　　所顯示為icl7135的數(shù)字部分。icl7135的引腳允許其方便地應(yīng)用在更復(fù)雜的系統(tǒng)。這些包括：</p><p>　　RUN/HOLD輸入（25腳）</p><p>　　當(dāng)RUN/HOLD端為高電平或開(kāi)路時(shí)。器件連續(xù)地每4000

96、2個(gè)時(shí)鐘脈沖完成測(cè)量周期。當(dāng)此輸入拉至低電平時(shí)，積分電路繼續(xù)完成正在進(jìn)行的測(cè)量周期。然后。只要引腳保持低電平，它便保持轉(zhuǎn)換的讀數(shù)。當(dāng)測(cè)量周期完成之后引腳保持低電平時(shí)。短的正脈沖(大于300ns)將啟動(dòng)新的測(cè)量周期，它的開(kāi)始以1和10001個(gè)計(jì)數(shù)脈沖的自動(dòng)歸零階段為準(zhǔn)。當(dāng)此正脈沖發(fā)生于測(cè)量周期（40002個(gè)脈沖）完成之前時(shí).它將不被識(shí)別。第一個(gè)STROBE脈沖發(fā)生于測(cè)量周期結(jié)束之后101計(jì)數(shù)處。它是測(cè)量周期完成的指示。因此。如果RUN/H

97、OLD為低電平，且在積分完成后第101個(gè)計(jì)數(shù)以后，即在第一個(gè)STROBE脈沖之后。正脈沖可用于觸發(fā)新的測(cè)量的開(kāi)始。</p><p>　　STROBE（26腳）</p><p>　　來(lái)自此輸入端的負(fù)向脈沖把BCD轉(zhuǎn)換數(shù)據(jù)傳送到外部鎖存器、UART或微處理器在測(cè)量周朝結(jié)束時(shí)。STROBE變?yōu)楦唠娖讲⒈３指唠娖竭_(dá)加201個(gè)計(jì)數(shù)值的時(shí)間，最高有效數(shù)字(MSD) BCD位放置在BCD端。</p

98、><p>　　在開(kāi)始101個(gè)計(jì)數(shù)之后。在輸出D1-5變?yōu)楦唠娖狡陂g內(nèi)的中途。STROBE變?yōu)榈碗娖竭_(dá)1/2時(shí)鐘脈沖寬度。在D5高電平脈沖的中間點(diǎn)放置STROBE脈沖允許用低電平或邊沿把信息鎖存入外部器件。這種STROBE脈沖的放置還確保第二個(gè)MSD的BCD位也不競(jìng)爭(zhēng)BCD線并且確保正確位的鎖存。對(duì)于第二個(gè)MSD和以D4輸出將重復(fù)以上過(guò)程。類似地。直至最低有效數(shù)字(LSD)將重復(fù)此過(guò)程。因此。輸入D5至D1和BCD線繼

99、續(xù)掃描而不包括STROBE脈沖。這種后續(xù)的連續(xù)掃描使轉(zhuǎn)換結(jié)果連續(xù)被顯示。當(dāng)超范圍( over-range )條件發(fā)生時(shí)，這種后續(xù)掃描將不發(fā)生。</p><p>　　BUSY (21腳)</p><p>　　在信號(hào)積分相開(kāi)始時(shí)BUSY(忙)輸出變?yōu)楦唠娖健USY將保持高電平直到零穿越(Zero crossing)之后的第一個(gè)時(shí)鐘脈沖或超范圍條件發(fā)生時(shí)的測(cè)量周朝結(jié)束時(shí)，利用BUSY端串行發(fā)送

100、轉(zhuǎn)換結(jié)果是可能的，通過(guò)把BUSY和CLOCK信號(hào)相“與”(AND)并發(fā)送“與”的結(jié)果使可完成串行發(fā)送。所發(fā)送的輸出包括發(fā)生在信號(hào)積分相內(nèi)10,001個(gè)時(shí)鐘脈沖以及發(fā)生在去積分(de —integrate )相期間內(nèi)的時(shí)鐘脈沖數(shù)。從總的時(shí)鐘脈沖數(shù)減去10001可以得到轉(zhuǎn)換結(jié)果。</p><p>　　OVERRANGE (27腳)</p><p>　　當(dāng)輸入信號(hào)大于2V滿量程時(shí)，該管腳信號(hào)變?yōu)?/p>

101、高電平。也就是說(shuō)，當(dāng)超范圍(over range)條件發(fā)生時(shí)，在測(cè)量周朝結(jié)束時(shí)BUSY(忙)信號(hào)變?yōu)榈碗娖街?，此引腳變?yōu)楦唠娖健Ｈ缜八?，?dāng)超范圍條件發(fā)生時(shí).BUSY(忙)信號(hào)將保持高電平直至測(cè)量周期結(jié)束為止。OVER RANGE(超范圍)輸出在BUSY(忙)結(jié)束時(shí)變?yōu)楦唠娖?。且在下一次測(cè)量周期的去積分(de integrate )相開(kāi)始時(shí)變?yōu)榈碗娖健?lt;/p><p>　　UNDERRANGE (28腳)<

102、;/p><p>　　當(dāng)轉(zhuǎn)換結(jié)果小于或等于滿度范圍的9%(1500個(gè)計(jì)數(shù))時(shí)。在BUSY(忙)信號(hào)結(jié)束時(shí)此引腳變?yōu)楦唠娖?。under-range(欠范圍)輸出在下一測(cè)量周期的信號(hào)積分相開(kāi)始時(shí)變?yōu)榈碗娖健?lt;/p><p>　　POLARlTY (23腳)</p><p>　　對(duì)于正輸入信號(hào)時(shí).POLARITY(極性)輸出為高電平。且在每一個(gè)去積分相的開(kāi)始處更新。換句話說(shuō)，對(duì)