ps2鼠標(biāo)鍵盤協(xié)議 外文翻譯

1、<p>　　畢業(yè)設(shè)計(jì)(論文)外文資料翻譯</p><p>　　學(xué) 院： 信息工程學(xué)院 </p><p>　　專 業(yè)： 通信工程092 </p><p>　　姓 名： 趙宏志 </p>

2、<p>　　學(xué) 號(hào)： 0906220242 </p><p>　　外文出處： www.computer-engineering.org </p><p>　　附 件： 1.外文資料翻譯譯文；2.外文原文。 </p><p>　　附件1：外文資料翻譯譯文&

3、lt;/p><p>　　PS2鼠標(biāo)鍵盤協(xié)議 </p><p>　　摘要：PS/2接口總線只使用數(shù)據(jù)線和時(shí)鐘線兩條導(dǎo)線來(lái)實(shí)現(xiàn)主機(jī)與設(shè)備的通訊，采用集電極開路實(shí)現(xiàn)了一種雙向同步串行協(xié)議。在總線空閑時(shí)，兩條線都是高電平。在這種狀態(tài)下，設(shè)備才允許開始傳輸數(shù)據(jù)。主機(jī)對(duì)總線有最高的控制權(quán)，在任何時(shí)候通過將時(shí)鐘線拉低就可以禁止設(shè)備通信。</p><p>　　關(guān)鍵詞：PS/2接口；數(shù)

4、據(jù)線；時(shí)鐘線；雙向同步串行協(xié)議</p><p><b>　　通訊：概述</b></p><p>　　PS / 2鼠標(biāo)和鍵盤實(shí)現(xiàn)雙向同步串行協(xié)議。該總線是“空閑”時(shí)，兩條線都高（集電極開路）。這是唯一的狀態(tài)下，鍵盤/鼠標(biāo)開始傳輸數(shù)據(jù)。主機(jī)總線擁有最終控制權(quán)，并可能抑制隨時(shí)溝通拉時(shí)鐘線低。該設(shè)備總是產(chǎn)生時(shí)鐘信號(hào)。如果主機(jī)要發(fā)送數(shù)據(jù)時(shí)，它必須先抑制通信設(shè)備拉動(dòng)時(shí)鐘低。主機(jī)然

5、后再換低和釋放時(shí)鐘數(shù)據(jù)。這是“請(qǐng)求發(fā)送”狀態(tài)和信號(hào)設(shè)備開始產(chǎn)生時(shí)鐘脈沖。</p><p>　　摘要：公交數(shù)據(jù)=高，時(shí)鐘=高： 空閑狀態(tài)。數(shù)據(jù)=高，時(shí)鐘=低： 通信抑制。數(shù)據(jù)=低，時(shí)鐘=高： 主機(jī)請(qǐng)求到發(fā)送</p><p>　　所有的數(shù)據(jù)都發(fā)送一個(gè)字節(jié)的時(shí)間的11-12位構(gòu)成一幀中發(fā)送的每個(gè)字節(jié)。這些位是：</p><p>　　1個(gè)起始位。始終為0。

6、</p><p>　　8個(gè)數(shù)據(jù)位，至少顯著位第一。</p><p>　　1個(gè)校驗(yàn)位（奇校驗(yàn)）。</p><p>　　1個(gè)停止位。這始終是1。</p><p>　　1，應(yīng)答位（僅主機(jī)到設(shè)備通信）</p><p>　　被設(shè)置，如果有偶數(shù)個(gè)1的數(shù)據(jù)位和復(fù)位（0），如果有一個(gè)數(shù)據(jù)位中的1的奇數(shù)奇偶校驗(yàn)位。數(shù)1的數(shù)據(jù)位加上校驗(yàn)位

7、總是加起來(lái)奇數(shù)（奇校驗(yàn)），這是用于錯(cuò)誤檢測(cè)。鍵盤/鼠標(biāo)必須檢查此位如果不正確的話，它應(yīng)該作出反應(yīng)，如果它已收到一個(gè)無(wú)效的命令。讀取從設(shè)備發(fā)送到主機(jī)的數(shù)據(jù)在時(shí)鐘信號(hào)的下降 邊緣上，從主機(jī)到設(shè)備發(fā)送的數(shù)據(jù)的上升沿讀取 時(shí)鐘的頻率必須在范圍10 - 16.7千赫。這意味著時(shí)鐘要高30 - 50微秒低30 - 50微秒..如果你設(shè)計(jì)一個(gè)鍵盤，鼠標(biāo)，或主機(jī)的模擬器，你應(yīng)該修改/采樣數(shù)據(jù)線在中間的每一個(gè)細(xì)胞。即15 - 25微秒后相應(yīng)的時(shí)鐘過渡

8、。同樣，鍵盤/鼠標(biāo)總是產(chǎn)生時(shí)鐘信號(hào)，但主機(jī)總是有通信的最終控制權(quán)。定時(shí)是絕對(duì)至關(guān)重要的。在這篇文章中我給每一個(gè)時(shí)間量必須嚴(yán)格遵守。</p><p>　　2.通訊：設(shè)備到主機(jī) 數(shù)據(jù)和時(shí)鐘線都是集電極開路。和+5 V的每一行之間的一個(gè)電阻連接，所以在總線的空閑狀態(tài)是高的。當(dāng)鍵盤或鼠標(biāo)要發(fā)送信息，它首先檢查時(shí)鐘線，以確保它是在一個(gè)較高的邏輯電平。如果不是的話，主機(jī)是抑制通信和設(shè)備必須緩沖任何將要發(fā)送的數(shù)據(jù)，直

9、到主機(jī)釋放時(shí)鐘。時(shí)鐘線必須持續(xù)至少50微秒之前的設(shè)備就可以開始傳輸數(shù)據(jù)。 </p><p>　　正如我在上一節(jié)中提到，鍵盤和鼠標(biāo)使用一個(gè)串行協(xié)議與11位幀。這些位是：</p><p>　　1個(gè)起始位。始終為0。</p><p>　　8個(gè)數(shù)據(jù)位，至少顯著位第一。</p><p>　　1個(gè)校驗(yàn)位（奇校驗(yàn)）。</p><p>

10、;　　1個(gè)停止位。這始終是1。</p><p>　　鍵盤/鼠標(biāo)寫入的數(shù)據(jù)線位鐘為高時(shí)，由主機(jī)時(shí)鐘是低時(shí)，它是只讀的。圖2和圖3示出了這一點(diǎn)。</p><p>　　圖2：設(shè)備到主機(jī)的通信。數(shù)據(jù)線改變狀態(tài)時(shí)，鐘為高時(shí)，時(shí)鐘是低，數(shù)據(jù)是有效的。 </p><p>　　圖3：“Q”鍵（15H）從鍵盤發(fā)送到計(jì)算機(jī)的掃描碼。通道A是時(shí)鐘信號(hào)通道B的數(shù)據(jù)信號(hào)。</p>

11、<p>　　--- 的時(shí)鐘頻率為10-16.7千赫。從一個(gè)時(shí)鐘脈沖的上升沿到數(shù)據(jù)轉(zhuǎn)換的時(shí)間必須是至少為5微秒。從數(shù)據(jù)轉(zhuǎn)換到一個(gè)時(shí)鐘脈沖的下降沿的時(shí)間必須是至少5微秒和不大于25微秒。主機(jī)可能抑制拉動(dòng)低時(shí)鐘線至少100微秒隨時(shí)溝通。如果傳輸被禁止前11個(gè)時(shí)鐘脈沖，該設(shè)備必須中止當(dāng)前的傳輸和準(zhǔn)備數(shù)據(jù)重傳的“塊”，當(dāng)主機(jī)釋放時(shí)鐘。一個(gè)“塊”的數(shù)據(jù)可能是一個(gè)品牌代碼，斷碼，設(shè)備ID，鼠標(biāo)運(yùn)動(dòng)包等，例如，如果鍵盤被中斷，同時(shí)發(fā)送兩

12、個(gè)字節(jié)的斷碼的第二個(gè)字節(jié)，就需要重傳兩個(gè)字節(jié)，斷碼，而不僅僅是一個(gè)被打斷。如果主機(jī)拉時(shí)鐘低之前，先高到低時(shí)鐘過渡，或者最后一個(gè)時(shí)鐘脈沖的下降沿后，鍵盤/鼠標(biāo)不需要重新傳輸任何數(shù)據(jù)。但是，如果新的數(shù)據(jù)被創(chuàng)建的，需要進(jìn)行傳輸時(shí)，它會(huì)被緩沖，直到主機(jī)發(fā)行時(shí)鐘。鍵盤有一個(gè)16字節(jié)的緩沖區(qū)用于此目的。如果發(fā)生價(jià)值超過16字節(jié)的按鍵，進(jìn)一步擊鍵將被忽略，直到緩沖區(qū)中有足夠的空間。小鼠只存儲(chǔ)最新的移動(dòng)數(shù)據(jù)包傳輸。</p><p&

13、gt;　　主機(jī)到設(shè)備的通訊 主機(jī)到設(shè)備通信數(shù)據(jù)包被發(fā)送一點(diǎn)點(diǎn)不同......</p><p>　　首先，PS / 2設(shè)備總是產(chǎn)生時(shí)鐘信號(hào)。如果主機(jī)要發(fā)送數(shù)據(jù)時(shí)，它必須首先把時(shí)鐘和數(shù)據(jù)線“請(qǐng)求發(fā)送”狀態(tài)如下：</p><p>　　禁止通信拉動(dòng)時(shí)鐘低至少100微秒。</p><p>　　應(yīng)用“請(qǐng)求發(fā)送”拉動(dòng)數(shù)據(jù)低，然后釋放時(shí)鐘。</p><

14、p>　　設(shè)備應(yīng)該檢查此狀態(tài)下，間隔不超過10毫秒。當(dāng)設(shè)備檢測(cè)到這種狀態(tài)下，它會(huì)開始產(chǎn)生時(shí)鐘信號(hào)和時(shí)鐘在8個(gè)數(shù)據(jù)位和1個(gè)停止位。主機(jī)改變了數(shù)據(jù)線，僅當(dāng)在時(shí)鐘線為低電平時(shí)，數(shù)據(jù)被讀時(shí)鐘為高時(shí)，由設(shè)備。這是相反的什么occours設(shè)備到主機(jī)的通信。</p><p>　　收到停止位后，設(shè)備將承認(rèn)接收到的字節(jié)，使數(shù)據(jù)線低，產(chǎn)生最后一個(gè)時(shí)鐘脈沖。如果主機(jī)不釋放數(shù)據(jù)線后的第11個(gè)時(shí)鐘脈沖，該設(shè)備將繼續(xù)產(chǎn)生時(shí)鐘脈沖直到數(shù)據(jù)

15、線被釋放（然后設(shè)備將產(chǎn)生一個(gè)錯(cuò)誤。）</p><p>　　主機(jī)可能中止傳輸時(shí)前11個(gè)時(shí)鐘脈沖應(yīng)答位時(shí)鐘線至少100微秒。</p><p>　　為了使這個(gè)過程變得更容易理解，這里的主機(jī)必須遵循的步驟將數(shù)據(jù)發(fā)送到一個(gè)PS / 2設(shè)備：</p><p>　　1）把時(shí)鐘線至少100微秒 2）把數(shù)據(jù)線低。3）釋放時(shí)鐘線。4）等待設(shè)備把時(shí)鐘線拉低 5）設(shè)置/復(fù)位數(shù)據(jù)線發(fā)

16、送第一個(gè)數(shù)據(jù)位 6）等待設(shè)備把時(shí)鐘拉高7）等待設(shè)備把時(shí)鐘拉低8）重復(fù)步驟5-7，其他7個(gè)數(shù)據(jù)位，校驗(yàn)位9）釋放數(shù)據(jù)線10）等待設(shè)備把數(shù)據(jù)線拉低11）等待設(shè)備把時(shí)鐘線拉低12）等待設(shè)備釋放數(shù)據(jù)線和時(shí)鐘</p><p>　　圖3用圖形表示，圖4的定時(shí)顯示由主機(jī)產(chǎn)生的信號(hào)，而生成的PS / 2設(shè)備分開。注意時(shí)機(jī)“確認(rèn)”位 - 數(shù)據(jù)改變發(fā)生時(shí)，時(shí)鐘線為高（而不是當(dāng)它是低，是其它11位的情況下的變化。）<

17、;/p><p>　　圖3：主機(jī)到設(shè)備的通訊。 </p><p>　　圖4：詳細(xì)的主機(jī)到設(shè)備通信。 </p><p>　　參考圖4，有兩個(gè)時(shí)間數(shù)量的主機(jī)看起來(lái)。（a）是所花費(fèi)的時(shí)間的移動(dòng)設(shè)備以開始產(chǎn)生時(shí)鐘脈沖后，主機(jī)最初需要的時(shí)鐘線為低，它必須是不大于15毫秒。（b）是所花費(fèi)的時(shí)間的數(shù)據(jù)包要發(fā)送，它必須是不大于2毫秒。如果不符合這些時(shí)間限制，主機(jī)應(yīng)產(chǎn)生一個(gè)錯(cuò)誤。

18、立即收到“確認(rèn)”后，主機(jī)可能會(huì)帶來(lái)抑制通信，數(shù)據(jù)處理，而它的時(shí)鐘線低。如果由主機(jī)發(fā)送的命令，需要一個(gè)響應(yīng)，該響應(yīng)必須不遲于20毫秒接收主機(jī)后釋放時(shí)鐘線。如果不會(huì)發(fā)生這種情況時(shí)，主機(jī)將生成一個(gè)錯(cuò)誤。</p><p>　　附件2：外文原文（復(fù)印件）</p><p>　　PS2 mouse and keyboard Agreement</p><p>　　Abstract

19、: PS / 2 interface bus using only two wires of the data and clock lines to host communication with the device, the use of open-collector to achieve a two-way synchronous serial protocol. The two lines are high when the b

20、us is idle. In this state, the device is only allowed to begin transmission of data. The highest level of control over the host bus, device communication can be disabled at any time by the clock line low.</p><

21、p>　　Keywords: PS / 2 interface; cable; clock line; bidirectional synchronous serial protocol</p><p>　　Communication: General Description</p><p>　　The PS/2 mouse and keyboard implement a bidir

22、ectional synchronous serial protocol. The bus is "idle" when both lines are high (open-collector). This is the only state where the keyboard/mouse is allowed begin transmitting data. The host has ultimate co

23、ntrol over the bus and may inhibit communication at any time by pulling the Clock line low. </p><p>　　The device always generates the clock signal. If the host wants to send data, it must first inhibit com

24、munication from the device by pulling Clock low. The host then pulls Data low and releases Clock. This is the "Request-to-Send" state and signals the device to start generating clock pulses.</p><p&

25、gt;　　Summary: Bus StatesData = high, Clock = high: Idle state.Data = high, Clock = low: Communication Inhibited.Data = low, Clock = high: Host Request-to-Send</p><p>　　All data is transmitted one byte

26、at a time and each byte is sent in a frame consisting of 11-12 bits. These bits are:1 start bit. This is always 0.</p><p>　　8 data bits, least significant bit first.</p><p>　　1 parity bit (odd

27、 parity).</p><p>　　1 stop bit. This is always 1.</p><p>　　1 acknowledge bit (host-to-device communication only)</p><p>　　The parity bit is set if there is an even number of 1's

28、 in the data bits and reset (0) if there is an odd number of 1's in the data bits. The number of 1's in the data bits plus the parity bit always add up to an odd number (odd parity.) This is used for error dete

29、ction. The keyboard/mouse must check this bit and if incorrect it should respond as if it had received an invalid command.Data sent from the device to the host is read on the falling edge of the clock signal; data sent

30、 from the hos</p><p>　　Timing is absolutely crucial. Every time quantity I give in this article must be followed exactly.Communication: Device-to-Host</p><p>　　The Data and Clock lines are bot

31、h open collector. A resistor is connected between each line and +5V, so the idle state of the bus is high. When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a

32、high logic level. If it's not, the host is inhibiting communication and the device must buffer any to-be-sent data until the host releases Clock. The Clock line must be continuously high for at least 50 microsecond

33、s before the device can begin to tra</p><p>　　As I mentioned in the previous section, the keyboard and mouse use a serial protocol with 11-bit frames. These bits are:</p><p>　　1 start bit. Thi

34、s is always 0.</p><p>　　8 data bits, least significant bit first.</p><p>　　1 parity bit (odd parity).</p><p>　　1 stop bit. This is always 1.</p><p>　　The keyboard/mous

35、e writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low. Figures 2 and 3 illustrate this.</p><p>　　Figure 2: Device-to-host communication. The Data line changes st

36、ate when Clock is high and that data is valid when Clock is low. </p><p>　　Figure 3: Scan code for the "Q" key (15h) being sent from a keyboard to the computer. Channel A is the Clock signal; ch

37、annel B is the Data signal.</p><p><b>　　--- </b></p><p>　　The clock frequency is 10-16.7 kHz. The time from the rising edge of a clock pulse to a Data transition must be at least 5

38、 microseconds. The time from a data transition to the falling edge of a clock pulse must be at least 5 microseconds and no greater than 25 microseconds. </p><p>　　The host may inhibit communication at any

39、time by pulling the Clock line low for at least 100 microseconds. If a transmission is inhibited before the 11th clock pulse, the device must abort the current transmission and prepare to retransmit the current "ch

40、unk" of data when host releases Clock. A "chunk" of data could be a make code, break code, device ID, mouse movement packet, etc. For example, if a keyboard is interrupted while sending the second byte o

41、f a two-byte break code, it will need </p><p>　　Host-to-Device Communication: The packet is sent a little differently in host-to-device communication...</p><p>　　First of all, the PS/2 dev

42、ice always generates the clock signal. If the host wants to send data, it must first put the Clock and Data lines in a "Request-to-send" state as follows:</p><p>　　Inhibit communication by pulling

43、 Clock low for at least 100 microseconds.</p><p>　　Apply "Request-to-send" by pulling Data low, then release Clock.</p><p>　　The device should check for this state at intervals not to

44、exceed 10 milliseconds. When the device detects this state, it will begin generating Clock signals and clock in eight data bits and one stop bit. The host changes the Data line only when the Clock line is low, and data

45、 is read by the device when Clock is high. This is opposite of what occours in device-to-host communication.After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and

46、 </p><p>　　The host may abort transmission at time before the 11th clock pulse (acknowledge bit) by holding Clock low for at least 100 microseconds.</p><p>　　To make this process a little easier

47、 to understand, here's the steps the host must follow to send data to a PS/2 device:</p><p>　　Bring the Clock line low for at least 100 microseconds. 2) Bring the Data line low. 3) Release the Cloc

48、k line. 4) Wait for the device to bring the Clock line low. 5) Set/reset the Data line to send the first data bit 6) Wait for the device to bring Clock high. 7) Wait for the device to bring Clock low. 8) R

49、epeat steps 5-7 for the other seven data bits and the parity bit 9) Release the Data line. 10) Wait for the device to bring Data low. 11) Wait for the device to bring</p><p>　　Figure 3 shows this graphi

50、cally and Figure 4 separates the timing to show which signals are generated by the host, and which are generated by the PS/2 device. Notice the change in timing for the "ack" bit--the data transition occours w

51、hen the Clock line is high (rather than when it is low as is the case for the other 11 bits.)</p><p>　　Figure 3: Host-to-Device Communication. </p><p>　　Figure 4: Detailed host-to-device com

52、munication. </p><p>　　Referring to Figure 4, there's two time quantities the host looks for. (a) is the time it takes the device to begin generating clock pulses after the host initially takes the Clo

53、ck line low, which must be no greater than 15 ms. (b) is the time it takes for the packet to be sent, which must be no greater than 2ms. If either of these time limits is not met, the host should generate an error. Im

54、mediately after the "ack" is received, the host may bring the Clock line low to inhibit communication</p><p>　　REFERENCES</p><p>　　[1] Daemen J,Rijmen V.The Design of Rijndael:AES-The

55、 Advanced Encryption Standard. . 2002</p><p>　　[2] Prof Stephen A,Edwards.The PS/2 Keyboard and Mouse Interface［D］Columbia University,2009:65-67</p><p>　　[3] PS/2 Mouse/Keyboard Protocol, [OL]

56、.Adam Chapweske, Copyright 1999:112-120.</p><p>　　[4] Holtek Semiconductor Inc.PS/2 Mouse Controller Data Sheet. . 2003</p><p>　　[5] Adam Chapweske.PS/2 Mouse/Keyboard Protocol. http://www.din.d