高級在軌系統(tǒng)幀同步接收器基于usb2.0總線的接口設計與開發(fā)

1、 （ 類 別 : 全 日 制 碩 士 研 究 生 全 日 制 碩 士 研 究 生 題 目 ： 高 級 在 軌 系 統(tǒng) 幀 同 步 接 收 器 基 于 目 ： 高 級 在 軌 系 統(tǒng) 幀 同 步 接 收 器 基 于U S B 2 . 0 總 線 的 接 口 設 計 與 開 發(fā) 總 線 的 接 口 設 計 與 開 發(fā) 英 文 題 目 ： 英 文 題 目 ： T h e D e s i g n a n d D e v

2、e l o p m e n t o f A O SF r a m e S y n c h r o R e c e i v e r ’ s I n t e r f a c eP o r t B a s e d o n U S B 2 . 0 B u s 研 究 生 ： 邢 自 茹 研 究 生 ： 邢 自 茹 學 科 名 稱 ： 計 算 機 應 用 技 術 學 科 名 稱 ： 計 算 機 應 用 技 術 指 導 教

3、師 ： 李 維 忠 副 教 授 指 導 教 師 ： 李 維 忠 副 教 授 二 ○ ○ 九 年 五 月 二 ○ ○ 九 年 五 月 碩 士 學 位 論 文 碩 士 學 位 論 文 分類號:學校代碼: 10128 分類號:學校代碼: 10128 U D C :學 號: 20061233 學 號: 20061233 Abstract The research of AOS standard become more

4、 and more important with the standard data of AOS adopted in international space technology step by step. Therefore, it is significant to develop AOS synchronous receiver for both the researches into the AOS standard and

5、 our country’s space technology. The study’s main work is the interface design of frame synchronization receiver based on the USB2.0 bus. The study realizes the communication between frame synchronous transceiver and hos

6、t based on USB2.0 bus. The whole system are finished on the YCL-USB2.0-FPGA development board, used Verilog HDL language under the Quarters environment and accomplished the transplanting of the frame synchronization rec

7、eiver from the FPGA based on PCI bus to the EP1C6Q240C8 chip based on USB bus. Since the interface of design of transmitter and receiver were carried at the same time, the author designed the assisted key modulation fram

8、e circuit, accomplished hardware-written-in data frame, which made the endpoint FIFO read effect data from FPGA, and assisted to complete the interface design of the receiver. The system uses GPIF Designer to carray out

9、GPIF waveform design for the programmable port of the CY7C68013A chip, thereby read the AOS data in the FIFO of FPGA chip. Under the μVision2 developing environment, we used Keil C51 to complete the firmware design of fr

10、ame synchronization receiver, which was loaded to E2PROM, thereby transported the FPGA data to PC through CY7C68013A chip. The problem that the length of AOS data frame is aliquant by 512 bytes was solved. The study acco

11、mplished the integration of frame synchronization receiver and transmitter in one card, and finished self-sending and self-receiving AOS standard data. The system accomplished plug and play and hot plug of frame synchron

12、ization receiver. AOS frame synchronization receiver can correctly receive the AOS standard data sent from another transmitter, so accomplished transmission of USB2.0 interface data. At last, tested by experiments, the

13、interface design of frame synchronization receiver has carried out the prospective design requirement. The transmission of data packet which is aliquant by 512 bytes was realized in the design, and has certain practical