全芯片設(shè)計(jì)高性能電驅(qū)動(dòng)熱點(diǎn)檢測(cè)的解決方案外文翻譯（英文）

1、High Performance Electrical Driven Hotspot Detection Solution for Full Chip Designusing a Novel Device Parameter Matching TechniqueRami F. Salem?, Mohamed Al-Imam?, Abdelrahman ElMously?, Haitham Eissa?, Ahmed Arafa?, an

2、d Mohab H. Anis? ?? Mentor Graphics Corporation ? ? The American University in CairoAbstract—With the continuous development of today’s technol- ogy, IC design becomes a more complex process. The designer now not only ta

3、kes care of the normal design and layout param- eters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the cur

4、rent process, schematic designers go through extensive simulations to cover all the possible variations of their design parameters and hence of the design functionality. At the same time, layout designers perform time-co

5、nsuming process-aware simulations (such as lithography simulations) on the full chip layout, which impacts the design turn-around time. In this paper, we present a fast physical layout- and electrical-aware Design-For-Ma

6、nufacturability (DFM) solu- tion that detects hotspot areas in the full chip design without requiring extensive electrical and process simulations. Novel algorithms are proposed to implement the engines that are used to

7、develop this solution. Our proposed flow is examined on a 45 nm industrial Finite Impulse Response (FIR) full chip. The proposed methodology is able to define a list of electrical hotspot devices located on the FIR criti

8、cal path that experience up to 17% variation in their DC current values due to the effect of process and design context. The total runtime needed to identify and detect these electrical hotspots on the FIR full chip take

9、s nearly 3 minutes, compared to hours when using conventional electrical and process simulations.Index Terms—Process variations, Design-For- Manufacturability (DFM), Lithography variations, Stress effects, Electrical Des

10、ign-For-Manufacturability (e-DFM), Parametric Yield, Hot spotsI. INTRODUCTIONAs technology migrates from 90nm down to 45nm, it is increasingly difficult to achieve fast yield ramp due to random defects, process variation

11、s, systematic yield problems, and other limitations referred to as design for manufacturing (DFM) issues. At 90nm and below, these problems often appear as layout hotspots. To avoid downstream yield and manufacturing pro

12、blems relating to layout hotspots, it is imper- ative that hotspots are addressed by different DFM techniques. Successful DFM techniques ensure high fabrication yield by incorporating manufacturability-aware models into

13、the design stage to identify and remove potentially problematic process hotspots. A typical DFM flow follows an incremental procedure, us- ing an embedded lithographic simulator for hotspot detection. Lithographic simula

14、tions [1] , [2] are precise yet costly to rundue to the complex calculations involved.are precise, yet costly to run, due to the complex calculations involved. Pattern Matching is another approach that allows design, man

15、ufacturing, and failure analysis teams to identify, isolate, and define problematic geometric configurations (patterns) directly from a design layout. Once recognized and defined, these patterns can be added to a pattern

16、 library that can be used to automatically scan designs for matching patterns, which can then be modified or removed. However, such techniques experience two major drawbacks: 1) Accuracy vs. Runtime tradeoff. The accurac

17、y of the pattern matching technique depends on the quality of the pattern library (i.e., the number of patterns identified and added into the library). However, too many patterns will lead to over-estimating potential ho

18、tspots, and directly increase the design flow runtime. 2) Purely geomtrical-based. Today’s pattern matching so- lutions are all based on geometrical recognition, which doesn’t distinguish those topologies that are electr

19、ically critical to the design.Elecrtical-driven DFM soultions have been proposed [3], [4] and [5] showing fair results and good performance, however these solutions were directed to reduce only lithography varia- tions b

20、y proposing performance-driven Optical Proximity Cor- rection (OPC) solutions and standard cell re-characterization.Fig. 1. From Layout to Spice Instance ParametersIn our paper, we propose a novel electrically-aware devi

21、ce parameter-based matching technique. The device parameters represented in the SPICE models contain different abstracts of information, such as the layout geometry, the design context978-1-4673-1036-9/12/$31.00 ©20

22、12 IEEE 223 13th Int'l Symposium on Quality Electronic DesignFig. 2. Proposed Design Context Aware and Electrical Driven DFM SolutionFig. 3. Device Parameters Matching F

23、lowB. Intent Driven Design EngineThe proposed engine (Figure 4), automatically gathers anno- tation and device/net information from the schematic netlist. This information is then processed to generate text, marker layer

24、s, or other geometry identification on the layout to mark the annotated devices/nets. The annotation type is combinedwith the text and marker layer numbers to generate specific rules based on the assigned annotations. Th

25、ese rules are then tested using Calibre tools [7] to determine if the intent was correctly interpreted and properly implemented on the physical layout design. Finally, the results are reported. An additional option uses

26、defined structures with Calibre PERC for topological matching.The flow can be divided into the following steps:1) Parsing the schematic annotations. The flow assumes that the front-end designer places annotations on the

27、schematic netlist in a certain format to inform the phys- ical layout engineers with critical devices/nets or that certain devices/nets have certain electrical constraints or should have special layout treatments This st

28、ep parses the annotations placed in the schematic netlist and identifies these annotations. 2) Linking the schematic database to the layout database. The second step links the parsed device/net to its corresponding mate

29、in the layout. The main link between the schematic netlist and the layout is the Layout vs. Schematic (LVS) rule deck. Running LVS on a design generates the cross-referencing database that links the device/net on the sch

30、ematic to its corresponding mate on the layout and provides the layout coordinates. 3) Marking the annotated devices and nets on the layout database. For device checks, the coordinates obtained from the cross-referencing

31、 files place a marking text layer on each appropriate device. However, because a complete net may be composed from many layers, one pair of coordinates is not enough to mark the net for net checks, so all net coordinates