單片機畢業(yè)設(shè)計外文翻譯--at89s52

1、<p>　　本科畢業(yè)設(shè)計（論文）外文翻譯</p><p><b>　　外文資料翻譯譯文</b></p><p><b>　　AT89S52</b></p><p><b>　　主要性能</b></p><p>　　與MCS-51單片機產(chǎn)品兼容</p>&

2、lt;p>　　8K字節(jié)在系統(tǒng)可編程Flash存儲器</p><p><b>　　1000次擦寫周期</b></p><p>　　全靜態(tài)操作：0Hz～33Hz</p><p><b>　　三級加密程序存儲器</b></p><p>　　32個可編程I/O口線</p><p&g

3、t;　　三個16位定時器/計數(shù)器</p><p><b>　　八個中斷源</b></p><p>　　全雙工UART串行通道</p><p>　　低功耗空閑和掉電模式</p><p><b>　　掉電后中斷可喚醒</b></p><p><b>　　看門狗定時器&l

4、t;/b></p><p><b>　　雙數(shù)據(jù)指針</b></p><p><b>　　掉電標識符</b></p><p><b>　　功能特性描述</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K在系統(tǒng)可編程Flash 存儲器

5、。使用Atmel公司高密度非易失性存儲器技術(shù)制造，與工業(yè)80C51產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8位CPU和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應(yīng)用系統(tǒng)提供高靈活、超有效的解決方案。AT89S52具有以下標準功能：8k字節(jié)Flash，256字節(jié)RAM，32位I/O口線，看門狗定時器，2個數(shù)據(jù)指針，三個16位定時器/計數(shù)器，一個6向量2級中斷

6、結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時鐘電路。另外，AT89S52可降至0Hz靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式?？臻e模式下，CPU停止工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)，單片機一切工作停止，直到下一個中斷或硬件復(fù)位為止。</p><p><b>　　引腳結(jié)構(gòu)</b></p><p><b>

7、　　方框圖</b></p><p><b>　　VCC : 電源</b></p><p><b>　　GND : 地</b></p><p>　　P0口：P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動8個TTL邏輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。當訪問外部程序和數(shù)據(jù)存儲器時，P0

8、口也被作為低8位地址/數(shù)據(jù)復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻。</p><p>　　在flash編程時，P0口也用來接收指令字節(jié)；在程序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。</p><p>　　P1口：P1 口是一個具有內(nèi)部上拉電阻的8位雙向I/O 口，p1 輸出緩沖器能驅(qū)動4個TTL 邏輯電平。對P1端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作

9、為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/計數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。在flash編程和校驗時，P1口接收低8位地址字節(jié)。</p><p>　　P2 口：P2 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2輸出緩沖器能驅(qū)動4個TTL 邏輯電平。對P2端口寫“1”時

10、，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲器或用16位地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR）時，P2口送出高八位地址。在這種應(yīng)用中，P2口使用很強的內(nèi)部上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器的內(nèi)容。</p><p>　　在flash編程和校驗時，P

11、2口也接收高8位地址字節(jié)和一些控制信號。</p><p>　　P3 口：P3口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，p2輸出緩沖器能驅(qū)動4個TTL 邏輯電平。對P3端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗時，P3口也接收一些

12、控制信號。</p><p>　　RST: 復(fù)位輸入。晶振工作時，RST腳持續(xù)2個機器周期高電平將使單片機復(fù)位?？撮T狗計時完成后，RST腳輸出96個晶振周期的高電平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認狀態(tài)下，復(fù)位高電平有效。</p><p>　　ALE/：地址鎖存控制信號（ALE）是訪問外部程序存儲器時，鎖存低8位地址的輸出脈沖。在flash

13、編程時，此引腳（）也用作編程輸入脈沖。</p><p>　　在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調(diào)，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。</p><p>　　如果需要，通過將地址為8EH的SFR的第0位置“1”，ALE操作將無效。這一位置“1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時有效。否則，ALE 將被微弱

14、拉高。這個ALE 使能標志位（地址為8EH的SFR的第0位）的設(shè)置對微控制器處于外部執(zhí)行模式下無效。</p><p>　　:外部程序存儲器選通信號（）是外部程序存儲器選通信號。</p><p>　　當 AT89S52從外部程序存儲器執(zhí)行外部代碼時，在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，將不被激活。</p><p>　　/VPP:訪問外部程序存儲器控制信

15、號。為使能從0000H 到FFFFH的外部程序存儲器讀取指令，必須接GND。</p><p>　　為了執(zhí)行內(nèi)部程序指令，應(yīng)該接VCC。</p><p>　　在flash編程期間，也接收12伏VPP電壓。</p><p>　　XTAL1:振蕩器反相放大器和內(nèi)部時鐘發(fā)生電路的輸入端。</p><p>　　XTAL2:振蕩器反相放大器的輸出端。&l

16、t;/p><p><b>　　存儲器結(jié)構(gòu)</b></p><p>　　MCS-51器件有單獨的程序存儲器和數(shù)據(jù)存儲器。外部程序存儲器和數(shù)據(jù)存儲器都可以64K尋址。</p><p>　　程序存儲器：如果引腳接地，程序讀取只從外部存儲器開始。</p><p>　　對于89S52，如果接VCC，程序讀寫先從內(nèi)部存儲器（地址為000

17、0H～1FFFH）開始，接著從外部尋址，尋址地址為：2000H~FFFFH。</p><p><b>　　中斷</b></p><p>　　AT89S52有6個中斷源：兩個外部中斷（和），三個定時中斷（定時器0、1、2）和一個串行中斷。這些中斷每個中斷源都可以通過置位或清除特殊寄存器IE中的相關(guān)中斷允許控制位分別使得中斷源有效或無效。IE還包括一個中斷允許總控制位EA

18、，它能一次禁止所有中斷。IE.6位是不可用的。對于AT89S52，IE.5位也是不能用的。用戶軟件不應(yīng)給這些位寫1。它們?yōu)锳T89系列新產(chǎn)品預(yù)留。</p><p>　　定時器2可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。程序進入中斷服務(wù)后，這些標志位都可以由硬件清0。實際上，中斷服務(wù)程序必須判定是否是TF2 或EXF2激活中斷，標志位也必須由軟件清0。</p><p>　　定時

19、器0和定時器1標志位TF0 和TF1在計數(shù)溢出的那個周期的S5P2被置位。它們的值一直到下一個周期被電路捕捉下來。然而，定時器2的標志位TF2在計數(shù)溢出的那個周期的S2P2被置位，在同一個周期被電路捕捉下來。</p><p><b>　　參考資料：</b></p><p>　　1．ATMEL公司AT89S52的技術(shù)手冊</p><p>　　2．

20、深圳市中源單片機發(fā)展有限公司AT89C52 Datasheets</p><p>　　3．復(fù)旦大學(xué)出版社單片微型機原理、應(yīng)用和實驗張友德等</p><p><b>　　外文原文</b></p><p><b>　　AT89S52</b></p><p><b>　　Features<

21、/b></p><p>　　? Compatible with MCS-51® Products</p><p>　　? 8K Bytes of In-System Programmable (ISP) Flash Memory</p><p>　　? 1000 Write/Erase Cycles</p><p>　　? F

22、ully Static Operation: 0 Hz to 33 MHz</p><p>　　? Three-level Program Memory Lock</p><p>　　? 256 x 8-bit Internal RAM</p><p>　　? 32 Programmable I/O Lines</p><p>　　? Thr

23、ee 16-bit Timer/Counters</p><p>　　? Eight Interrupt Sources</p><p>　　? Full Duplex UART Serial Channel</p><p>　　? Low-power Idle and Power-down Modes</p><p>　　? Interru

24、pt Recovery from Power-down Mode</p><p>　　? Watchdog Timer</p><p>　　? Dual Data Pointer</p><p>　　? Power-off Flag</p><p>　　Description</p><p>　　The AT89S5

25、2 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible wi

26、th the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU wit

27、h in system programmable Flash on a monolithicchip</p><p>　　Pin Configurations</p><p>　　Block Diagram</p><p>　　Pin Description</p><p><b>　　VCC</b></p>

28、<p>　　Supply voltage.</p><p><b>　　GND</b></p><p><b>　　Ground.</b></p><p><b>　　Port 0</b></p><p>　　Port 0 is an 8-bit open dra

29、in bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.</p><p>　　Port 0 can also be configured to

30、 be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.</p><p>　　Port 0 also receives the code bytes during Flash programmin

31、g and outputs the code bytes dur -ing program verification.External pullups are required during program veri- fication.</p><p><b>　　Port 1</b></p><p>　　Port 1 is an 8-bit bidirection

32、al I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins

33、 that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.</p><p>　　In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/

34、T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.</p><p>　　Port 1 also receives the low-order address bytes during Flash programming and verification.</p

35、><p><b>　　Port 2</b></p><p>　　Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pi

36、ns, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.</p><p>　　Port 2

37、 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups w

38、hen emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.</p><p>　　Port 2 also receives the high-order addr

39、ess bits and some control signals during Flash programming and verification.</p><p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port

40、3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,</p><p>　　Port 3 pins that are externally

41、 being pulled low will source current (IIL) because of the pullups. </p><p>　　Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.</p><p>

42、　　Port 3 also receives some control signals for Flash programming and verification.</p><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two machine cycles while the osci

43、llator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit D

44、ISRTO,the RESET HIGH out feature </p><p>　　is enabled.</p><p><b>　　ALE/</b></p><p>　　Address Latch Enable (ALE) is an output pulse for latching the low byte of the addre

45、ss during accesses to external memory. This pin is also the program pulse input () during Flash programming.</p><p>　　In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency a

46、nd may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.</p><p>　　If desired, ALE operation can be disabled by setting

47、 bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in extern

48、al execution mode.</p><p>　　Program Store Enable () is the read strobe to external program memory.</p><p>　　When the AT89S52 is executing code from external program memory, is activated twice ea

49、ch machine cycle, except that two activations are skipped during each access to external data memory.</p><p><b>　　/VPP </b></p><p>　　External Access Enable. must be strapped to GND

50、in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be ternally latched on reset. should be strapped to

51、 VCC for internal rogram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming.</p><p><b>　　XTAL1</b></p><p>　　Input to the inverting

52、 oscillator amplifier and input to the nternal clock operating circuit.</p><p><b>　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier.</p><p>　　Special F

53、unction Registers</p><p>　　A map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may n

54、ot be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.</p><p>　　User software should not write 1s to these u

55、nlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.</p><p>　　Timer 2 Registers: Control and status b

56、its are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-rel

57、oad mode.</p><p>　　Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.</p><p>　　

58、Timer 2 Operating Modes</p><p>　　In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is s

59、ampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following t

60、he one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required</p><p>　　Interrupts</p><p>　　The AT89S52 has a total of six interrupt vectors: two exte

61、rnal interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or dis

62、abled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which</p><p>　　disables all interrupts at once. Note that Table 5 shows that bit position IE.6 i

63、s unimplemented. In the AT89S52, bit position IE.5 is also unimplemented.</p><p>　　User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt

64、is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it

65、was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 </p><p>　　Reference data:</p><p>　　1.

66、the ATMEL company AT89S52 technical manuals</p><p>　　2.Shenzhen Development Co., Ltd. AT89C52 Datasheets source SCM</p><p>　　3.Fudan University Press, single-chip microprocessor theory, applicat