基于fpga的任意信號(hào)發(fā)生器設(shè)計(jì)外文翻譯

1、<p>　　基于FPGA的數(shù)字信號(hào)發(fā)生器的設(shè)計(jì)</p><p>　　在現(xiàn)代電子測(cè)量技術(shù)的研究及應(yīng)用領(lǐng)域中，常常需要高精度且參數(shù)可調(diào)的信號(hào)源。數(shù)字信號(hào)發(fā)生器已成為現(xiàn)代測(cè)量領(lǐng)域應(yīng)用最為廣泛的通用儀器之一，代表了信號(hào)源的發(fā)展方向。而隨著大規(guī)?？删幊踢壿嬈骷﨔PGA的發(fā)展以及可編程片上系統(tǒng)（SOPC）設(shè)計(jì)技術(shù)的日漸成熟，為這類信號(hào)發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)提供了理論依據(jù)與技術(shù)支持。本文設(shè)計(jì)的數(shù)字信號(hào)發(fā)生器以直接數(shù)字頻率

2、合成（DDS）技術(shù)為核心，用現(xiàn)場(chǎng)可編程門陣列（FPGA）來(lái)實(shí)現(xiàn)頻率和相位的預(yù)置和改變，并完成信號(hào)的頻率和相位差顯示。設(shè)計(jì)中采用的是直接數(shù)字頻率合成（DDS）技術(shù)，該技術(shù)是一項(xiàng)關(guān)鍵的數(shù)字技術(shù)，能很好的實(shí)現(xiàn)信號(hào)在幅度，頻率以及相位等方面的移動(dòng)。系統(tǒng)以EDA軟件為工具，采用VHDL語(yǔ)言，滿足了對(duì)數(shù)字信號(hào)控制的更高要求。結(jié)果表明，采用EDA技術(shù)設(shè)計(jì)的數(shù)字信號(hào)發(fā)生器使得數(shù)控系統(tǒng)與其他的電路實(shí)現(xiàn)的數(shù)字信號(hào)發(fā)生器相比具有更高的可靠性、實(shí)時(shí)性、運(yùn)算速度

3、高以及集成度高等特點(diǎn)。該數(shù)字信號(hào)發(fā)生器的設(shè)計(jì)可像軟件一樣隨時(shí)更改，這就為系統(tǒng)維護(hù)帶來(lái)了方便，同時(shí)結(jié)合FPGA有效地?cái)U(kuò)展輸出波形的頻率范圍，實(shí)現(xiàn)了輸出兩路高精度相位差的正弦信號(hào)，使系統(tǒng)性能穩(wěn)定可靠。</p><p>　　關(guān)鍵詞：信號(hào)發(fā)生器；DDS；片上可編程系統(tǒng)；FPGA；</p><p><b>　　1 導(dǎo)言</b></p><p>　　FPG

4、A本質(zhì)上是一種數(shù)字設(shè)備。然而，隨著FPGA的資源合理使用，使用FPGA進(jìn)行數(shù)字化多通道模擬波形成為了一種可能。數(shù)字化的波形可直接在FPGA內(nèi)部處理。目前有幾種模擬信號(hào)數(shù)字化的可能的方案。我們計(jì)劃在FPGA 模數(shù)轉(zhuǎn)換器的研究中使用一種基于在圖1所示的斜坡比較的方法。</p><p>　　圖1 基于FPGA的模數(shù)轉(zhuǎn)換器</p><p>　　模擬輸入均直接連接到FPGA的輸入引腳。一個(gè)無(wú)源RC網(wǎng)

5、絡(luò)連接到FPGA的輸出引腳，以便生成定期參考電壓斜坡。當(dāng)參考電壓斜坡到達(dá)輸入電壓等級(jí)時(shí)，差分輸入緩沖器被用作比較器來(lái)產(chǎn)生FPGA內(nèi)部邏輯轉(zhuǎn)換。轉(zhuǎn)換時(shí)間是通過(guò)TDC塊在FPGA中實(shí)現(xiàn)被數(shù)字化的。從這段時(shí)間以后，RC網(wǎng)絡(luò)參數(shù)和坡道起動(dòng)時(shí)間可以從已知的輸入電壓大小而得到。如今，F(xiàn)PGA器件被設(shè)計(jì)成與各種差分信號(hào)標(biāo)準(zhǔn)兼容以后，差分輸入緩沖器由于其有效的大的輸入電壓范圍成為了很好的比較器。許多基于比較器的ADC方案可以用FPGA來(lái)實(shí)現(xiàn)。例如，通過(guò)

6、計(jì)劃，在較大的FPGA資源使用下（通常是每通道4個(gè)I / O引腳），信號(hào)可以被迅速地跟蹤，并且只產(chǎn)生很小的數(shù)字化誤差。隨著威爾金森破敗的計(jì)劃，負(fù)責(zé)窄脈沖一體化可以用數(shù)字化來(lái)結(jié)合，盡管越來(lái)越多的外部模擬電路是必要的。我們?cè)诖搜芯康男逼卤容^方案（或者在分類借鑒基礎(chǔ)上的單斜坡ADC，盡管這兩個(gè)坡道的斜坡可以被利用）是對(duì)于相對(duì)緩慢的信號(hào)大通道數(shù)的應(yīng)用的一種合適的選擇。 （在一些參考資料里，單斜坡計(jì)劃被誤認(rèn)為是參照基于雙斜坡原則的威爾金森ADC。

7、）一個(gè)關(guān)鍵的功能塊，時(shí)間數(shù)字轉(zhuǎn)換器（TDC）在FPGA是需要的。有</p><p>　　在FPGA中的TDC已經(jīng)非常有用了。為費(fèi)米實(shí)驗(yàn)室MIPP升級(jí)項(xiàng)目設(shè)計(jì)的TDC卡在論文中也有記載。 多采樣結(jié)構(gòu)可以有其他的應(yīng)用。被熟知的“數(shù)字相位跟隨”（DPF）的解串器電路也有記載。使用DPF，任何FPGA輸入都可用于接收串行數(shù)據(jù)而無(wú)需專門的解串器，這些解串器只能由高端FPGA系列提供。該DPF可以補(bǔ)償由于電纜溫度的變

8、化或者由于晶體振蕩器發(fā)射機(jī)和接收機(jī)之間的頻率差而造成的輸入數(shù)據(jù)的相位漂移。</p><p>　　2 TDC在FPGA中的運(yùn)行</p><p>　　在FPGA中的TDC是基于多相位時(shí)鐘的。TDC的輸入是通過(guò)四個(gè)寄存器被采樣的，這些寄存器有四個(gè)相位的時(shí)鐘。如圖2所示。</p><p>　　圖2 多抽樣的TDC電路</p><p>　　輸入被緩沖，

9、然后以同樣的傳播延遲發(fā)送到四個(gè)寄存器。這四個(gè)寄存器連接到有90°相位差的四個(gè)內(nèi)部時(shí)鐘上。0度和90度的時(shí)鐘通過(guò)相鎖回路（PLL）時(shí)鐘合成器產(chǎn)生。他們的倒置用于產(chǎn)生180度和270度的時(shí)鐘。根據(jù)到達(dá)時(shí)間，有關(guān)的輸入邏輯電平轉(zhuǎn)換被記錄在不同地點(diǎn)的四個(gè)寄存器內(nèi)。我們?cè)贏ltera的Cyclone FPGA器件設(shè)備（EP1C6Q240C6）使用的時(shí)鐘頻率是360兆赫，它提供了0.69納秒（LSB）的時(shí)間分辨率。一個(gè)單相的時(shí)鐘域轉(zhuǎn)移出現(xiàn)

10、在第二和第三個(gè)記錄層。然后輸入信號(hào)的到達(dá)時(shí)間是編碼為兩個(gè)時(shí)間位（T0和T1）和一個(gè)數(shù)據(jù)有效信號(hào)（DV），計(jì)數(shù)器提供了一個(gè)命令時(shí)位。</p><p>　　過(guò)渡邊緣檢測(cè)和脈沖濾波邏輯都包含在編碼器內(nèi)。對(duì)于許多應(yīng)用程序，一個(gè)簡(jiǎn)單的領(lǐng)先優(yōu)勢(shì)編碼就足夠了。例如在一些應(yīng)用中，從一電線室估計(jì)輸入脈沖，前緣和后緣都可以數(shù)字化。在這種情況下，一個(gè)額外的輸出顯示邊緣的類型可能會(huì)需要。該脈沖濾波功能可以防止輸入電路鈴聲由于被錯(cuò)誤數(shù)字化

11、而造成的超短脈沖。我們?cè)O(shè)計(jì)到連續(xù)四個(gè)位的位量子點(diǎn)至Q3模式使用了通過(guò)查找表的FPGA邏輯單元，以確定一個(gè)采樣點(diǎn)是否在一個(gè)完善的脈沖邊緣?；叵胍幌率褂貌檎冶淼腇PGA，它可以實(shí)現(xiàn)“任何“四個(gè)輸入的組合邏輯，滿足邊緣檢測(cè)和脈沖過(guò)濾的應(yīng)用要求。</p><p>　　時(shí)序關(guān)鍵的信號(hào)通路通過(guò)設(shè)置輸入緩沖區(qū)來(lái)控制，多采樣寄存器和FPGA的內(nèi)部時(shí)鐘域轉(zhuǎn)移寄存器如圖3所示。這種對(duì)稱的布局，保證從輸入緩沖區(qū)到采樣寄存器的一致的傳播

12、延遲，從而獲得均勻的位寬，最大限度地減少微分非線性。</p><p>　　圖3 FPGA中的時(shí)序關(guān)鍵路徑 </p><p>　　邏輯元件布局由“手動(dòng)“的電子數(shù)據(jù)表完成。所有的TDC通道（每通道約10項(xiàng)）在輸入緩沖區(qū)和觸發(fā)器的位置都被保存在電子表格。在Cyclone FPGA器件中，四個(gè)通道都被集中在五個(gè)邏輯陣列塊（LAB）里，如上面所示。設(shè)計(jì)者可能會(huì)進(jìn)一步安排好每一個(gè)4通道組的位置去不斷調(diào)

13、整從輸入引腳的輸入延遲組，便于使不同群體的傾斜通道的最小化。試算表是編碼到輸出一個(gè)ASCII的文件，這個(gè)文件粘貼到為Quartus II與Altera FPGA設(shè)計(jì)軟件的編制的指定文件中。</p><p>　　3 基于FPGA的模數(shù)轉(zhuǎn)換器測(cè)試結(jié)果</p><p>　　FPGA的ADC的幾次試驗(yàn)已經(jīng)完成，如圖1所示電路。具有兩個(gè)值集的R1，R2和C來(lái)實(shí)現(xiàn)斜坡參考電壓不同的時(shí)間常數(shù)。</

14、p><p><b>　　線性參考電壓擬</b></p><p>　　在第一次配置，R1的值為50歐姆，R2為100歐姆，C =1000pF。FPGA用切換率為11.25 MHz，3.3V的差分電壓驅(qū)動(dòng)RC網(wǎng)絡(luò)。該參考電壓幾乎是一個(gè)沒(méi)有太多指數(shù)功能的三角波。輸入到ADC的電壓和參考電壓的示波器的波形如圖4所示。ADC的輸入是四個(gè)不同寬度和峰值振幅的脈沖序列。</p&g

15、t;<p>　　圖4 ADC輸入（藍(lán)色）輸入和參考電壓（黑色）</p><p>　　輸入信號(hào)是由參考電壓每88ns在兩次開(kāi)頭和結(jié)尾的坡道和每一次穿過(guò)坡道創(chuàng)建的一個(gè)由TDC數(shù)字化的翻轉(zhuǎn)邊緣。采樣率大約是每秒采樣22.5兆，??（雖然前端和后斜采樣點(diǎn)的采樣間隔是不一樣的）。轉(zhuǎn)換時(shí)期前端和后斜道的采樣是由6位的測(cè)量范圍的TDC來(lái)數(shù)字化的。 TDC的原始數(shù)據(jù)都顯示在圖5（a）中。轉(zhuǎn)換時(shí)間進(jìn)一步轉(zhuǎn)化為輸入電壓

16、的水平，如圖5（b）所示。</p><p>　　圖5 （a）TDC的原始數(shù)據(jù) (b)數(shù)字化波形</p><p>　　應(yīng)當(dāng)指出，TDC的值不僅僅代表著采樣點(diǎn)的電壓水平，而且還代表著采樣時(shí)間。在高精度應(yīng)用中，采樣時(shí)間的分歧應(yīng)該予以考慮，但這不是太困難的事。</p><p>　　B、指數(shù)參考電壓 RC網(wǎng)絡(luò)的放電性能指數(shù)，可用于提高ADC的動(dòng)態(tài)范圍。在第二個(gè)配置

17、中，R1的值為50歐姆，R2為100歐姆，電容C為150pF。參考電壓如圖6所示，它有一個(gè)很短的時(shí)間常數(shù)。</p><p>　　圖6 參考電壓的放電性能指數(shù)</p><p>　　該指數(shù)樣本的輸入?yún)⒖茧妷翰ㄐ稳鐖D7（a）所示。（請(qǐng)注意，圖6和圖7（a）的示波器時(shí)間尺度不同，但它們的電壓表是相同的。）由圖7（b）可以看出，一個(gè)平滑的波形通過(guò)尾隨的坡道被數(shù)字化了。該測(cè)試展示了一個(gè)以22.5兆每秒

18、的采樣速率的6位的測(cè)量范圍，而樣本的尾部坡道動(dòng)態(tài)范圍大約是8位。</p><p>　　圖7 （a）輸入波形（b）數(shù)字化波形</p><p>　　被動(dòng)元件被選擇為下一代網(wǎng)絡(luò)的參考電壓斜坡，主要是為了簡(jiǎn)單。被動(dòng)的RC網(wǎng)絡(luò)的斜坡電壓在本質(zhì)上是非線性，這在有時(shí)被認(rèn)為是一種缺陷。然而，在FPGA種，糾正非線性僅僅是通過(guò)查表來(lái)進(jìn)行變換的。在我們的例子中，指數(shù)電壓斜坡可進(jìn)一步用于增加測(cè)量的動(dòng)態(tài)范圍，這已

19、經(jīng)成為一種優(yōu)勢(shì)。 在許多應(yīng)用中，測(cè)量時(shí)只需要相對(duì)精度，也就是說(shuō)，精細(xì)測(cè)量只應(yīng)用在小信號(hào)中，而對(duì)大信號(hào)來(lái)說(shuō)，粗精度的測(cè)量已經(jīng)足夠了。</p><p><b>　　4 總結(jié)</b></p><p>　　研究了基于TDC的多采樣，實(shí)施了低成本FPGA和測(cè)試臺(tái)的三個(gè)應(yīng)用：僅TDC下的多通道的FPGA， 僅在 ADC下的FPGA和一個(gè)解串器“數(shù)字相位跟隨器”的討論。FP

20、GA接口直接與連續(xù)變量（抵達(dá)時(shí)間和輸入電壓）相接，單TDC的多通道FPGA， 單 ADC的FPGA和一個(gè)解串器“數(shù)字相位跟隨器” 三個(gè)應(yīng)用正在討論中。FPGA與連續(xù)變量（抵達(dá)時(shí)間和輸入電壓）直接相接，可以消除外部設(shè)備，并簡(jiǎn)化系統(tǒng)設(shè)計(jì)。這種測(cè)量的實(shí)現(xiàn)可立即在FPGA中處理，而無(wú)需通過(guò)總線上的數(shù)據(jù)。</p><p>　　The Design of Digital Signal Generator Based on F

21、PGA </p><p>　　Signal sources with high accuracy and operational frequency are used in the field of research and application of modern electronic measuring technology. Digital signal represent the development

22、 with it being one of the most widely measuring technology in the field. With the development of FPGA in a large scale and the maturing of SOPC, design technology have provided theoretical basis and technology support fo

23、r the design and realization of such signal generators. This design of digital signal g</p><p>　　Keywords: signal generator; DDS; System On a Programmable Chip; The FPGA</p><p>　　I. INTRODUCTION

24、</p><p>　　FPGA is a digital device. However, with suitable use of the FPGA resources, it is possible to use FPGA to digitize multi-channel analog waveforms. The digitized waveforms can be directly processes

25、in the FPGA. There are several possible schemes of digitizing analog signals. One of the schemes we used in our FPGA ADC study is based on the ramping-comparing approach as shown in Fig.1.</p><p>　　The analo

26、g inputs are directly connected to the FPGA input pins. A passive RC network is connected to the FPGA output pins so that a periodic reference voltage ramp can be generated. The differential input buffers are used as com

27、parators to generate logic transitions inside the FPGA when the reference voltage ramps across the input voltage levels. The transition times are digitized by the TDC block implemented in the FPGA. Since the period, the

28、RC network parameters and the starting time of the </p><p>　　In today’s FPGA devices, differential input buffers are good comparators within a sufficiently large range of input voltage levels, since they are

29、 designed to be compatible with various signaling standards. Many comparator-based ADC schemes can be implemented with FPGA. For example, with the delta-sigma scheme. the signal can be tracked promptly yielding smaller d

30、igitization errors at a cost of higher FPGA resource usage (typically, 4 I/O pins per channel). With Wilkinson rundown scheme, charge </p><p>　　A key functional block, Time-to-Digit-Converter (TDC) is neede

31、d in FPGA. There are two TDC schemes that can be implemented in FPGA: delay chain scheme and multisampling scheme . The TDC we used in this work is multisampling scheme with quad clock as in Reference . In Reference , fo

32、ur sets of sample, edge detect, pulse filter and count latch are driven by four clocks with 90o phase separations. These four sets of data collected by four sets of circuits are excessive and they become valid at diff<

33、;/p><p>　　The TDC in FPGA alone is already very useful. The TDC card designed for Fermilab MIPP upgrade project is documented in this paper.</p><p>　　The multi-sampling structure can have other app

34、lications. A deserializer circuit known as “Digital Phase Follower” (DPF) is also documented. Using DPF, any FPGA input can be used to receive serial data without needing dedicated deserializer that is only available in

35、high-end FPGA families. The DPF can compensate input data phase drift not only due to cable temperature variation, but also due to crystal oscillator frequency difference between transmitter and receiver.</p><

36、p>　　II. TDC IMPLEMENTED IN FPGA</p><p>　　The TDC inside the FPGA is based on multi-phased clock. The input of the TDC is sampled by four registers with four phases of the clock as shown in Fig. 2</p>

37、;<p><b>　　..</b></p><p>　　The input is buffered, and then sent to four registers with equal propagation delays. The four registers are connected to four internal clocks each with 90o phase

38、 difference. The 0o and 90o clocks are generated by the phase-lock-loop (PLL) clock synthesizer and their inversions are used for 180o and 270o clocks. Depending on arrival time, the transitions of the input logic level

39、s are recorded at different locations within the four registers. The clock frequency used in our Altera Cyclone FPGA d</p><p>　　Transition edge detection and pulse filtering logics are included in the encode

40、r. For many applications, a simple leading edge encoding is sufficient. In some applications, for example, to estimate input pulse charge from a wire chamber, both leading and trailing edges may be digitized. An addition

41、al output indicating the type of edge may be needed in this case. The function of pulse filtering prevents ultra short pulses due to input circuit ringing from being mistakenly digitized. In our design</p><p&g

42、t;　　Timing critical signal paths are controlled by placing the input buffer, multi-sampling registers and clock domain transfer registers in the FPGA as shown in Fig. 3. This symmetric placement assures equal propagation

43、 delays from input buffer to the sampling registers, resulting in uniform bit widths and thus minimizes differential non-linearity.</p><p>　　The logic element layout is done “manually” with a spread sheet. T

44、he locations of the input buffer and flip-flops, (about 10 items per channel) for all TDC channels are kept in the spread sheet. In Cyclone FPGA devices, four channels are grouped together in five logic array blocks (LAB

45、) as shown above. The designer may further arrange the location of each four-channel group to adjust the input delay from input pin to the group so that the skews between different channel groups are minimized. The</p

46、><p>　　III. TEST RESULTS OF FPGA BASED ADC</p><p>　　Several tests of FPGA ADC are done with circuits shown in Fig. 1 with two sets of values of R1, R2 and C to achieve different time constants for

47、the ramping reference voltage..</p><p>　　A. Quasi-linear Reference Voltage</p><p>　　In the first configuration, the values of R1 = 50, R2 = 100 and C = 1000pF. The FPGA drives the RC network wit

48、h a toggling rate of 11.25 MHz in differential 3.3V level. The reference voltage is nearly a triangle wave with not much exponential feature. The oscilloscope traces of the input voltage to the ADC and the reference volt

49、age are shown in Fig. 4. The input to ADC is a sequence of four pulses with different widths and peak amplitudes.</p><p>　　The input signal is crossed by the reference voltage twice every 88ns by both leadin

50、g and trailing ramps and each crossing creates a flipping edge that is digitized by the TDC. The sampling rate is approximately 22.5 M samples/sec, (although the sampling intervals between the points sampled by the leadi

51、ng and trailing ramps are not the same). The transition times sampled by both the leading and trailing ramps are digitized by the TDC with 6-bit measurement range. The raw TDC data are shown in Fi</p><p>　　I

52、t should be pointed out that the TDC values represent not only the voltage levels at the sampling points, but also the sampling times. In high precision applications, the differences of the sampling times should be taken

53、 into account but it is not too difficult to do so.</p><p>　　B. Exponential Reference Voltage</p><p>　　The exponential discharge property of the RC networks can be used to increase the dynamic r

54、ange of the ADC. In the second configuration, the values of R1 = 50, R2 = 100 and C = 150pF. The reference voltage shown in Fig. 6 has a short time constant.</p><p>　　The exponential reference voltage sample

55、s the input waveform shown in Fig. 7(a). (Note that the oscilloscope time scales for Fig. 6 and 7(a) are different but the voltage scales are them same.) It can be seen from Fig. 7(b) that a smoother waveform is digitize

56、d by the trailing ramp. This test shows a 6- bit measurement range at 22.5 M samples/sec while the dynamic range of the trailing ramp samples is approximately 8 bits.</p><p>　　Passive components are chosen f

57、or the ramping reference voltage generation network primarily for simplicity. The ramping voltage from passive RC network is intrinsically nonlinear which sometimes is viewed as a disadvantage. In FPGA, however, correcti

58、ng nonlinearity is merely a transform via a look-up table. In our example here, the exponential voltage ramp can be further used to increase measurement dynamic range, which becomes an advantage.</p><p>　　In

59、 many applications, only relative precision in a measurement is needed, i.e., finer measurements are only needed for small signals while for larger signals, coarser measurements are sufficient.</p><p>　　IV.

60、CONCLUSION</p><p>　　Multi-sampling based TDC has been studied, implemented in low cost FPGA and bench tested.</p><p>　　Three applications: multi-channel FPGA-only TDC, FPGA only ADC and a deseri

61、alizer “Digital Phase Follower” are discussed. Interfacing FPGA directly with the continuous variables (arrival time and input voltage) eliminates external devices and simplifies system design. The measurement made can b

62、e processed immediately in the FPGA without having to pass data via on board busses.</p><p>　　REFERENCES</p><p>　　[1] P. Allen & D. Holberg, CMOS Analog Circuit Design, Second Edition, New Y

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70、;p>　　[8] Altera Corp., “Cyclone FPGA Family Data Sheet”, (2003) available via: {http://www.altera.com/}</p><p>　　[9] Altera Corporation, “Cyclone II Device Handbook”, (2007) available via: {http://www.alt

71、era.com/}</p><p>　　[10] Jinyuan Wu, “Digital Phase Follower -- Deserializer in Low-Cost FPGA”, BTeV Document 3295-v1, Fermi National Accelerator Laboratory, (2004), available online: {http://www-btev.fnal.go

72、v/cgibin/ public/DocDB/ShowDocument?docid=3295}</p><p>　　[11] Nick Sawyer, “Data Recovery”, Xilinx Application Note 224, v2.5 (2005), available via: {http://www.xilinx.com}</p><p>　　[12] Jinyuan