外文翻譯---一種新型通用全數(shù)字時(shí)鐘勻滑技術(shù)

1、<p><b>　　翻譯（中）</b></p><p>　　一種新型通用全數(shù)字時(shí)鐘勻滑技術(shù)</p><p>　　秦曉懿,王瀚晟,曾烈光</p><p>　　(清華大學(xué)電子工程系微波與數(shù)字通信技術(shù)國家重點(diǎn)實(shí)驗(yàn)室.北京100084)</p><p>　　摘要: 針對(duì)鎖相環(huán)在勻滑含有低頻大幅度的抖動(dòng)和漂移的時(shí)鐘時(shí)有諸

2、如同步和捕捉范圍很窄?容易失鎖等缺點(diǎn),提出了一種新的全數(shù)字時(shí)鐘勻滑技術(shù)——統(tǒng)計(jì)預(yù)測(cè)法.其主要思想是用一個(gè)周期的統(tǒng)計(jì)結(jié)果來預(yù)測(cè)下一個(gè)周期的處理值從該方法的原理和性能分析可知,其可有效的勻滑各種抖動(dòng)和漂移.抖動(dòng)積累較小,同步和捕捉范圍很寬,可以勻滑不同頻率的時(shí)鐘.另外,改進(jìn)的變周期的統(tǒng)計(jì)預(yù)測(cè)法也可使捕捉時(shí)間降到合適的長度,以適用于不同場合.</p><p>　　關(guān)鍵詞: 時(shí)鐘勻滑技術(shù);抖動(dòng);漂移;統(tǒng)計(jì)預(yù)測(cè)法</

3、p><p>　　中圖分類號(hào): TN913.24, TN914.3 </p><p><b>　　文獻(xiàn)標(biāo)識(shí)碼: A </b></p><p>　　文章編號(hào): 0372-2112(2001)09-1276-04</p><p><b>　　1.引言</b></p><p>　　傳統(tǒng)的

4、時(shí)鐘勻滑技術(shù)一般采用鎖相環(huán),但要濾出頻率較低?幅度較大的抖動(dòng)甚至漂移,鎖相環(huán)的帶寬需要很窄(如要求小于十分之幾Hz甚至更小).此時(shí)模擬鎖相環(huán)的元件尺寸將變得過大而難以實(shí)現(xiàn).同時(shí),窄帶寬的鎖相環(huán)其同步范圍和捕捉范圍常常很小.在初始情況或非正常情況下容易由于較大的瞬時(shí)頻差或相差而失鎖鎖相環(huán)能勻滑的時(shí)鐘頻率僅在中心頻率附近的范周內(nèi).同一設(shè)計(jì)難于勻滑不同速率.另外,鎖相環(huán)是用輸入?輸出時(shí)鐘的相位差來對(duì)VCO頻率進(jìn)行調(diào)整,當(dāng)輸入時(shí)鐘抖動(dòng)較大,由于

5、輸出時(shí)鐘受到輸入時(shí)鐘的影響,兩者的相位差并不能準(zhǔn)確的反映輸人時(shí)鐘的情況,輸入時(shí)鐘的抖動(dòng)容易傳遞到輸出時(shí)鐘上,從而增加抖動(dòng)的積累.本文則提出了一種新的通用時(shí)鐘勻滑技術(shù)——統(tǒng)計(jì)預(yù)測(cè)法.該方法可有效勻滑各種抖動(dòng)或漂移,抖動(dòng)積累較小,同步范圍和捕捉范圍很寬,可以對(duì)不同頻率進(jìn)行勻滑,并可全數(shù)字實(shí)現(xiàn),便于集成.</p><p><b>　　2.基本原理</b></p><p>　

6、　圍1為統(tǒng)計(jì)預(yù)測(cè)法的原理框圖.圖中寫時(shí)鐘是待勻滑的時(shí)鐘,讀時(shí)鐘為勻滑后的時(shí)鐘.統(tǒng)汁周期控制可與寫時(shí)鐘或高速時(shí)鐘相關(guān).周期統(tǒng)計(jì)計(jì)數(shù)通過對(duì)一個(gè)周期內(nèi)寫時(shí)鐘或其信息與高速時(shí)鐘的關(guān)系的統(tǒng)計(jì),預(yù)測(cè)出下一個(gè)周期應(yīng)扣除的高速時(shí)鐘脈沖個(gè)數(shù)(對(duì)采用扣除值的電路而言,一般為電路實(shí)現(xiàn)方便,高速時(shí)鐘選得比讀時(shí)鐘的r倍高,以避免有增加高速時(shí)鐘脈沖的操作)或應(yīng)生成的時(shí)鐘脈沖個(gè)數(shù).周期統(tǒng)計(jì)計(jì)數(shù)在具體實(shí)現(xiàn)時(shí)可有多種方案,例如:(1)由高速時(shí)鐘產(chǎn)生與寫時(shí)鐘標(biāo)稱頻率相同的

7、固定參考時(shí)鐘,周期統(tǒng)計(jì)計(jì)數(shù)模塊統(tǒng)計(jì)出一個(gè)周期內(nèi)固定參考時(shí)鐘與寫時(shí)鐘的個(gè)數(shù)差異來預(yù)測(cè)時(shí)鐘扣除值或生成值;(2)直接對(duì)一個(gè)周期內(nèi)的寫時(shí)鐘個(gè)數(shù)進(jìn)行統(tǒng)計(jì),則下一個(gè)周期的預(yù)測(cè)生成值為寫時(shí)鐘個(gè)數(shù)統(tǒng)計(jì)值的r倍.當(dāng)統(tǒng)計(jì)周期足夠大時(shí),可以認(rèn)為相鄰周期內(nèi)寫時(shí)鐘的情況近似相等,因此可將前一周期的統(tǒng)計(jì)值作為后一周期的預(yù)測(cè)值.時(shí)鐘綜合模塊則隨周期統(tǒng)計(jì)計(jì)數(shù)輸出的扣除值或生成值進(jìn)行對(duì)應(yīng)的扣除操作或生成操作(如圖2所示).圖中時(shí)鐘扣除的功能為扣除脈沖上每有一個(gè)脈沖,則

8、扣除高速時(shí)鐘的一個(gè)脈沖.為得到高質(zhì)量(低抖動(dòng)和漂移)的時(shí)鐘.通常有兩種策略:(1)使扣除脈沖或生成脈沖的位置盡量均勻分布,</p><p>　　在緩沖存儲(chǔ)器中,通過比較讀時(shí)鐘與寫時(shí)鐘的相位差來給出相應(yīng)的溢出或取空指示,以提前或延后讀時(shí)鐘的相位例如對(duì)扣除值而言,溢出指示將控制時(shí)鐘綜合模塊,瞬時(shí)地減少扣除一個(gè)高速時(shí)鐘脈沖,使讀時(shí)鐘的相位前移1/r UI;反之,取空指示則瞬時(shí)地增加扣除一個(gè)高速時(shí)鐘脈沖.該過程是為了調(diào)整

9、緩沖存儲(chǔ)器中寫數(shù)據(jù)與讀數(shù)據(jù)之間的初始相對(duì)位置,因此只有在初始狀態(tài)或非正常狀態(tài)下,才可能送出溢出或取空指示,其它狀態(tài)下并不發(fā)生這個(gè)過程.故其對(duì)抖動(dòng)和漂移的分析不會(huì)產(chǎn)生影響.若不需得到與勻滑后時(shí)鐘同步的數(shù)據(jù)時(shí).圖l中虛線框內(nèi)的部分可以略去.</p><p>　　當(dāng)周期統(tǒng)計(jì)計(jì)數(shù)模塊采用第一種方案時(shí),統(tǒng)計(jì)預(yù)測(cè)法與鎖相環(huán)結(jié)構(gòu)很相似,但其本質(zhì)差別在于:鎖相環(huán)是根據(jù)讀寫時(shí)鐘的相位差異來改變讀時(shí)鐘,用讀寫時(shí)鐘的相位差作為控制只能

10、使讀時(shí)鐘能跟蹤寫時(shí)鐘的變化,若寫時(shí)鐘有短時(shí)的較大幅度的躍變,讀時(shí)鐘的相位抖動(dòng)也容易隨之增大,因此并小能很好的抑制抖動(dòng)和漂移.而統(tǒng)計(jì)預(yù)測(cè)法則根據(jù)寫時(shí)鐘與固定參考時(shí)鐘的頻率差異來產(chǎn)生讀時(shí)鐘,其更能如實(shí)的反映寫時(shí)鐘的變化,因此抖動(dòng)積累更小一些.</p><p>　　另外,當(dāng)要?jiǎng)蚧臅r(shí)鐘頻率較高時(shí),高速時(shí)鐘的頻率可能會(huì)過高,以致在集成電路中難以實(shí)現(xiàn).此時(shí),可將對(duì)高速時(shí)鐘的處理改為對(duì)幾個(gè)頻率相同?相位不同的較低頻時(shí)鐘的處理

11、例如，設(shè)高速時(shí)鐘頻率為,則改為對(duì)頻率為/r,相位依次落后l/r UI的r個(gè)時(shí)鐘進(jìn)行處理.通過對(duì)r個(gè)時(shí)鐘的切換，實(shí)現(xiàn)對(duì)相位的滯后與超前控制,相當(dāng)于對(duì)高速時(shí)鐘的扣除與增加操作.當(dāng)將切換為(0≤i≤r-1)時(shí),相當(dāng)于相位滯后l/r UI;當(dāng)將切換為時(shí),相當(dāng)于相位超前l(fā)/r UI;讀時(shí)鐘的抖動(dòng)仍約為l/r UI.</p><p><b>　　3.結(jié)語</b></p><p>

12、　　統(tǒng)計(jì)預(yù)測(cè)法作為一種通用的時(shí)鐘勻滑技術(shù)，可以有效的濾出低頻、大幅度的抖動(dòng)或漂移、且其具有鎖相環(huán)電路沒有的一些優(yōu)點(diǎn)：抖動(dòng)積累更??；在獲得好的性能的同時(shí)，同步和捕捉范圍仍然很寬，可對(duì)不同頻率的時(shí)鐘進(jìn)行勻滑.另外，變周期的統(tǒng)計(jì)預(yù)測(cè)法也可使捕捉時(shí)間降到合適的長度，以應(yīng)用于不同場合.</p><p>　　附錄4 翻譯（英）</p><p>　　A New Universal All-Digita

13、l Clock Smoothness Technique</p><p>　　QIN Xiao-yi, WANG Han-sheng, ZENG Lie-guang</p><p>　　(State Key Laboratory on Microwave &&Digital Communication, Department of Electronic Engineerin

14、g, Tsinghua University, Beijing 100084, China)</p><p>　　Abstract: As pulls have some disadvantages such as the narrow synchronizing and pull-in ranges to smooth clocks with low-frequency large-amplitude jitt

15、er and wander, this paper presents a novel universal digital clock smoothness technique—the counting prognostication method. The key element of this technique is to use counting results in a cycle to prognosticate number

16、s in the next cycle. Principles and performance analyses are given to show that it can efficiently smooth jitter and wander, jitt</p><p>　　Key words: clock smoothness techniques; jitter; wander; counting pro

17、gnostication</p><p>　　Document code: A </p><p>　　Article ID: 0372-2112 (2001) 09-1276-04 </p><p>　　1. Introduction </p><p>　　Smoothing by traditional clock PLL is typi

18、cally used, but filter out low frequency, large amplitude jitter or drift, take a very narrow bandwidth phase-locked loop (if requested less than a few tenths of Hz or less). At this time analog PLL components size will

19、become too large and difficult to achieve. Meanwhile, the narrow bandwidth of the PLL capture range and scope of its synchronization is often very small. In normal circumstances, the initial conditions or easily as the l

20、arger instantaneou</p><p>　　2. Basic principles </p><p>　　Circuit 1 is a block diagram of statistical prediction. The figure was to be smoothing the clock is the clock, read clock to the clock

21、after smoothing. Statistically cycle control may be related write clock or high-speed clock cycle by cycle counting statistics clock or to write a letter.</p><p>　　The relationship between income and high-sp

22、eed clock statistics, predict the next cycle should be deducted from the number of high-speed clock pulse (on the use of net value of the circuit, the circuit is generally convenient, high-speed clock selection read cloc

23、k r times than high in order to avoid an increase in operating high-speed clock pulse) or the number of clock pulses to be generated. cycle counting statistics can be realized in a variety of specific programs, such as:

24、(1) written by a </p><p>　　In the buffer memory, by comparing the read clock and write clock phase to give the corresponding overflow or take air directions to advance or delay the phase of clock time the va

25、lue of such deduction, the overflow direct control of the clock synthesis module reduce the deduction of a transient high-speed clock pulse, the phase of the clock forward to reading 1 / r UI; the other hand, means to ta

26、ke an empty net of currency is a transient increase in high-speed clock pulse. Adjustment of the pro</p><p>　　When the cycle count statistics with the first program module, the statistical prediction method

27、and the phase-locked loop structure is similar, but the essential difference is: read and write clock PLL is based on the phase difference to change the time clock, the clock used to read and write phase as the control c

28、an only read the clock to track the write clock changes, if the clock for short time to write more substantial jump, read the clock phase jitter is also easy to increase with and, the</p><p>　　In addition, w

29、hen the smoothing higher clock frequency, high-speed clock frequency may be too high, resulting in the integrated circuit is difficult to achieve. At this point, the treatment can change the clock speed will be on the sa

30、me number of frequency, phase difference The low-frequency clock processing, for example, setting high-speed clock frequency, the frequency was changed to r, followed by backward phase l/r UI r-clock processing. r clock

31、by switching to realize the phase lag and adva</p><p>　　3. Conclusion </p><p>　　Statistical prediction method as a universal clock smoothing technique can effectively filter out low frequency, s

32、ignificant jitter or drift, and it has a phase-locked loop circuit without some of the advantages: a smaller jitter accumulation; to get good performance at the same time, synchronization, and capture still very wide ran