基于h.264的幀內(nèi)預(yù)測(cè)解碼器ip核的設(shè)計(jì)

1、北京航空航天大學(xué)碩士學(xué)位論文基于H.264的幀內(nèi)預(yù)測(cè)解碼器IP核的設(shè)計(jì)姓名：張哲申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：計(jì)算機(jī)應(yīng)用技術(shù)指導(dǎo)教師：艾明晶20070307Abstract ii Abstract H.264 is the video coding standard developed by ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Grou

2、p, which achieves enhanced compression performance and provides a “network-friendly” video representation. However, these advances are abtained at the cost of increased computational complexity which is 2-3 times than MP

3、EG-4. That means the performance of software decoding can not achieve a high level. Hardware accelerator or appropriative hardware decoing circuit is needed in this case. On the research of H.264 standard, this paper pro

4、poses an architecture fit for H.264 intra prediction arithmetic which adopts mixed data flow path and pipe-line and adopts mixed synchronization and communication strategy of centralized and disperse control. This paper

5、analizes the design method of reusable technologies and reuses the modules of similar arithmetic. According to the characteristic of H.264, this paper improves traditional line storage mechanism and improves the utilizin

6、g rate of chip storage resource by 80 percents. This paper optimizes CAVLC decoder. The using storage space saving the code table is very close to that in theory. A new quick combining arithmethc is proposed to combine t

7、he level and Runbefor once the Runbefore decoding completes. A new parallel register group architecture is proposed to combine the zig-zag into CAVLC decoding and read one block datas in one cycle Finally, this paper com

8、pletes the design of Intra Prediction Decoder Based On H.264 which can decode two kind of video format-CIF and QCIF in real-time with Verilog HDL. The theory and experiment both indicate that the decoder designed by this