外文翻譯--基于3gpp-lte標(biāo)準(zhǔn)的并行turbo碼解碼器asic設(shè)計(jì)與實(shí)現(xiàn)（英文）

1、See discussions, stats, and author profiles for this publication at: http://www.researchgate.net/publication/224182170Design and Implementation of a ParallelTurbo-Decoder ASIC for 3GPP-LTEARTICLE in IEEE JOURNAL OF SOL

2、ID-STATE CIRCUITS · FEBRUARY 2011Impact Factor: 3.11 · DOI: 10.1109/JSSC.2010.2075390 · Source: IEEE XploreCITATIONS32DOWNLOADS405VIEWS2024 AUTHORS, INCLUDING:Christoph StuderCornell University86 PUBLICATI

3、ONS 873 CITATIONS SEE PROFILEAvailable from: Christoph StuderRetrieved on: 16 June 20152 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1, JANUARY 2011Fig. 1. Left: parallel-concatenated turbo-encoder. Right: sim

4、plified block-diagram of a turbo-decoder.Fig. 2. Left: radix-2 forward state-metric recursion for two trellis-steps. Right: radix-4 forward state-metric recursion.over the wireless channel. In the receiver, a soft-output

5、 detector computes reliability information in the form of log-likelihood ratios (LLRs) for the transmitted bits , and [8]; the resulting LLRs , and indicate the probability of the corresponding bits being a binary 1 or 0

6、.A. Turbo-Decoding AlgorithmDecoding of turbo-codes is usually performed with the algo- rithm proposed in [8]. The main idea is depicted on the right- hand side (RHS) of Fig. 1 and amounts to iteratively exchanging extri

7、nsic LLRs and between the two SISO decoders (SDs) to improve the error-rate performance successively. The first and second SD perform decoding of the convolutional code generated by the first or the second CE, respective

8、ly. One pass by both the first and the second SD is referred to as a full-iter- ation; the operation performed by a single SD a half-iteration. The total number of full-iterations for each code block is de- noted by (e.g

9、., 11 half-iterations correspond to ). Each SD computes intrinsic a-posteriori LLRs and , for the transmitted bits, based on the systematic LLRs in naturalor interleaved order , on the parity LLRs or ,and on the so-calle

10、d a-priori LLRs or . For the first half-iteration, the a-priori LLRs are set to zero (i.e.,, ). In subsequent iterations, each SD uses the extrinsic LLRs computed by the other SD in the previous half-iteration as a-prior

11、i LLRs, i.e.,and (see Fig. 1). After a givennumber of half-iterations, the turbo-decoder generates estimates for the information bits based on the sign of the intrinsic LLRs.B. Radix-4 Max-Log M-BCJR AlgorithmThe maximum

12、 a-posteriori (MAP) SISO decoding algorithm developed by Bahl, Cocke, Jelinek, and Raviv (BCJR) [9] forms the basis of the SD used in this work. The BCJR algorithm re- sembles the Viterbi algorithm [10] and traverses a t

13、rellis rep- resenting the convolutional code to compute the intrinsic LLRs. Fig. 2 shows such a trellis, with nodes corresponding to the states of the CEs and branches indicating admissible state- transitions. Each trans

14、ition from a state (trellis-step ) to (trellis-step ) is associated with a branch-metric(refer to [11], [12] for details). The BCJR algorithm in its orig- inal form is impractical due to large memory requirements and the

15、 computation of transcendental functions. We adopt an ap- proximate algorithm [11], [13], as briefly described below. 1) Max-Log Approximation: The BCJR algorithm traverses the trellis in both forward and backward direct

16、ions to compute the state-metrics and recursively for all eight states. To avoid transcendental functions, we apply the max-log ap- proximation to the forward state-metric recursions [11](1) where and correspond to the t