系統(tǒng)芯片中媒體增強(qiáng)數(shù)字信號(hào)處理器核設(shè)計(jì)研究.pdf

1、浙江大學(xué)博士學(xué)位論文系統(tǒng)芯片中媒體增強(qiáng)數(shù)字信號(hào)處理器核設(shè)計(jì)研究姓名：李東曉申請(qǐng)學(xué)位級(jí)別：博士專業(yè)：通信與信息系統(tǒng)指導(dǎo)教師：姚慶棟20040101塑堅(jiān)點(diǎn)蘭豎主蘭些堡塞ABSTRACTHowtoutilizetheavailablehardwareresourcesoothesiliconchipeffectivelyisakeyissueinhighperformance／costmediasystem—on—chip(SoC)devel

2、opmentAbussharedheterogeneousarchitectureconsistingofoneormoreinstructionsetprocessorcores，oneormorededicatedhardwareIPcoresandoneormoreonchipmemoriesusuallyprovidesagoodsolutionTheresearchworkintroducedinthispapermainly

3、concernstheprocessorcoredesignformediaSueMediaenhancementbackwardextensiontoMIPSIcompatible1SAispresentedinthispaperBasedontheanalysisofinherentcharacteristicsofmediaapplicationalgorithms，thebasicMIPSIcompatibleISAisexte

4、ndedtosupportsubwordparallelSIMDoperation，specialresulthandling，anddedicatedmediainstructionsThemediaenhancementextensiontoMIPS—IcompatibleISAisphysicallyrealizedintheprocessorcore，andimprovesmediaprocessingperformanceef

5、fectively(2—4x)withnegligibleadditionalhardwarecost(27％)AFiniteStateMachine(FSM)basedcentralizedcontrolschemeispresentedinthispapertosupervisetheCPUpipelineactivityAndsomeeffectivetechniquesarediscussedtolowertheclockper

6、iodandCPI(CyclesPerInstruction)ofthepipelineToeliminatetheclockfrequencylimitationbysomecomplexinstructions’longexecutingtimeandachievesinglecyclethroughput，ascalablesuperpipeliningextensiontechniquetogetherwithahighperf

7、ormance／costpipelineshiftmechanismispresentedinthispaperForsingleissueprocessorarchitecture，theradicalsolutiontoCPIreductionistodeceasepipelinestallsexploitingavailablesoftwareorhardwaretechniquesARAW(ReadAfterWrite)depe

8、ndencyloopmodelisdevelopedinthispapertoanalyzetheRAWhazardsofregisteroperandsincomplexpipelineBasedonthismodel，a“dynamic’’dataforwardingpolicyissuggestedteducethepipelinestallscausedbydataRAWhazardsTheoreticalanalysisand

9、practicalexperimentsbothshowthattheaverageCPIincrementcausedbydataRAWhazardscanbereducedeffectivelybythedynamicdataforwardingstrategyBusdesignandmediadatastreamschedulingarekeyissuesinrealtimemediaSoCdevelopmentDatasched

10、ulingpoliciesforMPEG1／2videodecodingisdiscussedinthispaperaccordingtosoftwareorhardwareimplementationcaseTwo3framesgrainedschedulingpoliciesaresuggestedtomakegoodtradeoffbetweenprocessingdemandsandonchipbufferdemandsinso

11、ftwaredecodingimplementationAstatictimedivisionmultiplexedscheduling／dynamicfixedpriorityarbitrationbased2levelhybridarbitrationscheme，incorporatedwithsynchronjzationcontrol，isintroducedinthispapertoutilizethebusbandwidt