外文翻譯---微機系統(tǒng)

1、<p><b>　　中文2330字</b></p><p>　　THE MICROPROCESSOR SYSTEM</p><p>　　A microprocessor system can be described at a number of different levels of complexity. The least complex from i

2、s that of a simple block diagram describing the interconnection and flow of information functional blocks and will be used to examine the operation of a microprocessor system.</p><p>　　All microprocessor sys

3、tems contain a central processing unit(CPU),program and</p><p>　　data memory and input(I/O) devices.Fig.4-4 show a block diagram of a typical</p><p>　　embedded microprocessor system in which eac

4、h block corresponds roughly to the individual integrated circuit(chip) used in the system.</p><p>　　The memory section contains both non-volatile read only memory(ROM) as program memory and volatile random a

5、ccess memory(RAM) as read/write data memory .For each type of memory there are a number of different types of devices ,such as erasable ROMs and static or dynamic RAMs, each of which is chosen for an application based on

6、 its cost and function. </p><p>　　Four different I/O functions are shown in Fig.4-4.An analogue input channel to the microprocessor system is provided by the analogue to digital(A/D) converter and may be use

7、d to connect a device such as an analogue to digital(A/D) converter and may be used to connect a device such as an analogue sensor. An analogue output channel is provided by the digital to analogue(D/A) converter and cou

8、ld be used to control an output transducer such as an electric motor, The parallel I/O device provides a nu</p><p>　　The level and power specifications of the interfacing signals of the microprocessor system

9、 are frequently incompatible with the signal specifications of the devices which are to be interfaced to it .For example, the output voltage of a D/A converter may typically be in the range 0-5 volts and be capable of su

10、pplying only a few milliamperes of current,</p><p>　　Fig.4-4 Block diagram of a typical embedded microprocessor system</p><p>　　while the electric motor may require a control voltage range of pl

11、us and minus 12 volts at a maximum current of 1 ampere. Consequently, additional analogue interface circuitry is often necessary to perform functions such as signal level shifting, amplification and filtering.</p>

12、<p>　　Fig.4-4 also shows there peripheral circuits: an input control unit(ICU),a programmable counter/timer, and a direct memory access unit(DMA).All this devices are interfaced to the CPU by means of a system bus

13、which is itself made up from an address bus and a control bus. Physically, a bus is simple a collection of parallel interconnections between to or more devices. The number of lines contained in each bus is dependent on t

14、he type of microprocessor used in the system and the function of the bus</p><p>　　The concepts of address and data are fundamental to the operation of a stored program computer and form a feature of all micr

15、oprocessors and computers. The memory will consist of a number of memory locations capable of storing data written to them by the CPU over the data bus .Each memory location is uniquely identified to the CPU by a number

16、called its address. The CPU controls the address and control bus lines in order to write or read information to or form the memory or I/O devices. For exam</p><p>　　A similar procedure would be used if the C

17、PU was then to read a memory address, except this the flow of data would be from the memory to the CPU. After the CPU had placed the address of the required memory location on to the address bus .it would indicate to the

18、 memory that it wished to read the value by activating the relevant line in the control bus .The memory would respond by placing the contents of the memory location ad data on to the data bus ,and this would then be read

19、 by the CPU.</p><p>　　Within the system bus, the address bus is an output bus from the CPU and an input bus to the other devices. The control bus consists of a number of lines, each of which may be either a

20、control output from the CPU or a control input to the CPU. The data bus however acts as both an input bus and an output bus depending on whether the CPU is reading or writing data.Fig.4-4 shows that all devices in the sy

21、stem are connected together by the data bus and this means that, potentially at least, the outp</p><p>　　In the example of Fig.4-4 the data bus has eight lines, and hence the range of values which a single i

22、tem of data can take is restricted to that which can be represented by 8 binary digits or bits. Eight bits are referred to as a byte, and can represent a decimal number from 0 to 255;Likewise the address bus ,consisting

23、of sixteen lines, can represent an address number in the range 0 to 65535.This number is usually abbreviated to the binary equivalent of the decimal number and expressed as 64K,w</p><p>　　The CPU will contai

24、n a number of registers which are used to manipulate the data and its addresses. In the example chosen, these data registers will be 8 bit registers and all data manipulations will be performed on 8 bit quantities. The C

25、PU is therefore referred to as an 8 bit CPU, However, registers which support address manipulations need to be 16 bit registers because of the 16 bit address bus. The size of the address bus is independent of the size of

26、 the data bus ,so that 16 bit or 32 bit C</p><p>　　It is normal when working with microprocessors to represent binary numbers as hexadecimal (base 16) values, because a single hexadecimal hex)digit correspon

27、ds to a group of four consecutive binary <digits.>The hexadecimal number is easier to read and write than its binary equivalent, and it requires only simple mental calculation in order to translate from hexadecimal

28、 to binary and back again. Hexadecimal numbers and digits are identified in the text by prefixing them with Ox, which is the conve</p><p>　　It is not necessary for the hardware designer to make use of the en

29、tire address range of the CPU, and the physical memory required can be implemented anywhere within the address space of the CPU. In addition, the I/O devices will contain registers through which the I\O devices may be co

30、nfigured, and which provide addresses through which the CPU can read and write data into and out of the system. These registers appear to the CPU. as normal memory location. And so occupy parts of the address spac</p&

31、gt;<p>　　The memory map will be designed to meet the requirements of the application, and will be used by the hardware designer to partition the address space so that the address range of the memory devices in the

32、 system corresponds to the address range specified by the memory map. This is achieved by means of the address decoder. Shown in Fig.19-1,this uses lines from the address bus as its input and produces individual chip sel

33、ect signals for each chip which contributes to the memory map of the system.</p><p>　　RAM enable =A.15 A.14 A13.A12=A15+A14+A13+A12 (4-4) </p><p>　　as in Fig.4-5b.</p><p>　　From<

34、;Technical English for mechanical engineering>.Direction Editor Zhangyue. China machine press.1.2003</p><p><b>　　參考譯文 ：</b></p><p><b>　　微機系統(tǒng)</b></p><p>　　

35、微機系統(tǒng)可在許多復雜的層面上進行描述。最簡單的形式是用簡單的方塊圖來描述內(nèi)部的連接以及各功能塊間的信息流，并用來分析微機系統(tǒng)的工作情況。</p><p>　　所有微機系統(tǒng)包含一個中央處理單元（CPU）、程序和數(shù)據(jù)存儲器以及輸入、輸出（I/O）設備。圖4-4表示了一個典型的嵌入式微機系統(tǒng)的方框圖，該圖中每個方塊大致上對應于該系統(tǒng)中所用的單個集成電路（芯片）。</p><p>　　存儲器部分包

36、含了用作程序存儲器的掉電不易失信息的只讀存儲器（ROM）和用作讀/寫的掉電易失的隨機訪問數(shù)據(jù)存儲器（RAM），每種存儲器都有許多不同類型的元件，如可擦寫的ROM以及靜態(tài)或動態(tài)RAM，應用時，根據(jù)價格、功能來選擇。</p><p>　　圖4-4表示四種不同的I/O功能，微機系統(tǒng)的模擬信道由模數(shù)（A/D）轉(zhuǎn)換提供，可以連接如模擬輸入傳感器這樣的器件。模擬輸入信道由數(shù)模（D/A）轉(zhuǎn)換器提供，可以用于控制像電動機這樣的動

37、力輸出轉(zhuǎn)換器。并行I/O元件提供許多獨立的輸入/輸出端口線，在輸出方式下，這些端口可以通過編程提供邏輯電平1或0來驅(qū)動二進制（開/關）設備如燈泡。在 輸入方式下，微處理器可允許讀入開關及其他的二進制設備的狀態(tài)。串行I/O設備用于與其他的微機系統(tǒng)或不同操作模式的操作控制臺之間進行通信。</p><p>　　微機系統(tǒng)接口信號的電平和功率大小，常常與連接的元器件不匹配，例如，一個D/A轉(zhuǎn)換器典型的輸出電壓是0～5V ，

38、并僅能提供毫安培級電流，而電動機可能要求的控制電壓范圍為-12V～+12V，最大電流1A。為此需相應的增加模擬接口電路實現(xiàn)信號電平轉(zhuǎn)換、放大和濾波。圖4-4中還表示了三個外圍電路：中斷控制單元（ICU）、可編程計數(shù)/定時器以及直接存儲器訪問單元（DMA）。</p><p>　　所有這些元件都通過系統(tǒng)總線和CPU接口。系統(tǒng)總線由地址總線、數(shù)據(jù)總線和控制總線構成。實際上，總線只是兩個元件間并行連接線的集合。每個總線包

39、含的引線由系統(tǒng)使用的微處理器的型號以及總線的功能來確定，如圖4-4所示，我們假設地址總線為16根，數(shù)據(jù)總線為8根，控制總線數(shù)目不確定，這要由CPU提供的功能而定。</p><p>　　地址和數(shù)據(jù)是運行計算機所儲存的程序、形成所有微處理器和計算機特征的基礎。存儲器由許多能由CPU通過數(shù)據(jù)總線寫入數(shù)據(jù)的存儲單元構成。每個存儲單元具體位置由CPU用地址來唯一標識。為了從存儲器或I/O口設備中寫或讀信息，CPU控制著地址

40、和控制總線，如CPU希望將二進制信息01010101寫入地址為0000000000001111的存儲單元，CPU首先將該地址送到地址總線上，然后將01010101作為數(shù)據(jù)送到數(shù)據(jù)總線上，控制總線中的控制線激活，啟動數(shù)字寫入適當?shù)拇鎯卧?。相類似的情況用于CPU只讀存儲單元的地址的過程，這時數(shù)據(jù)流不是從存儲器到CPU，那么在CPU將要求的存儲單元的地址送到地址總線上后，CPU通過啟動控制總線相關的控制線，指示存儲器要讀數(shù)據(jù)，存儲器則做出反

41、應，將該存儲單元的內(nèi)容當作數(shù)據(jù)，送上數(shù)據(jù)總線，然后CPU讀取到該數(shù)據(jù)。</p><p>　　在系統(tǒng)總線中，地址總線對CPU來說是輸出總線，但對其他設備是輸入總線，控制總線包含許多線，它們或者是CPU輸出控制線，或者是輸入控制線。數(shù)據(jù)總線既當作輸入總線，又作輸出總線，這要看CPU是讀還是寫數(shù)據(jù)，圖4-4，表示了系統(tǒng)中所有元件都通過數(shù)據(jù)總線連在一起，這意味著，最低限度上存儲器和I/O設備的 輸出是連在一起的。如果實際

42、情況是這樣，則將引起所有連接的元件中幾個或全部元件被破壞，因為一些元器件將試圖驅(qū)動總線到邏輯1狀態(tài)，而其他一些則試圖驅(qū)動其為0狀態(tài)。為了避免這個問題，連接到每個元件的數(shù)據(jù)總線有第三種狀態(tài)即高阻態(tài)，在這種狀態(tài)下元件對總線不再有負載的影響，這就使連接到數(shù)據(jù)總線上的其他元件在需要時能將數(shù)據(jù)送上數(shù)據(jù)總線，這也就意味著在某一時刻僅有一個元件與數(shù)據(jù)總線相通。一個元件處于數(shù)據(jù)總線的邏輯1、邏輯0或高阻態(tài)稱為三態(tài)。這是共享相同的數(shù)據(jù)總線的設備很重要的特

43、性。</p><p>　　在圖4-4的例子中，數(shù)據(jù)總線為8根，因此能得到的單個數(shù)據(jù)被8位二進制數(shù)所限制，八位指一個字節(jié)，能代表從0～2555的十進制數(shù)；同樣地，地址總線包含16根線，能代表的地址范圍從0～65535，這個數(shù)字常常被縮寫成與二進制等價的十進制數(shù)，表示成64K，1K在二進制系統(tǒng)中等于1024，對于CPU而言，系統(tǒng)就像一連串的64K的連續(xù)的存儲單元，每個單元可存放一個八位二進制數(shù)。</p>

44、<p>　　CPU包含許多寄存器，他們用于處理數(shù)據(jù)和地址，在所選擇的例子中，這些數(shù)據(jù)寄存器為8位的寄存器，所有的數(shù)據(jù)操作都是8位，因此CPU就指8位COU，但是支持地址操作的寄存器需16位，因為地址總線是16位的。地址總線的寬度是獨立的，因此16位或32位CPU典型的有16位、24位或32位地址總線。</p><p>　　通常對微處理操作時用16進制（基于16）值代表二進制數(shù)，因為一個十六進制（hex

45、）數(shù)與四位連續(xù)的二進制數(shù)相對應。十六進制數(shù)比相等的二進制數(shù)易讀寫，并且只需簡單的換算就能將十六進制數(shù)與二進制數(shù)互譯，十六進制元數(shù)在文本中是用前綴ox標識，這是在C編程語言中所采用的，例如，16位二進制數(shù)1111110100111001寫成十六進制的形式為oxFD39。</p><p>　　硬件設計者沒有必要利用CPU的整個地址空間，所要求的物理存儲器可以在CPU的地址空間中任何一處。另外，I/O設備包含寄存器，通

46、過它們可對I/O設備進行設置，并為CPU提供讀寫數(shù)據(jù)的地址。這些寄存器對CPU來說就是普通的存儲單元，因此要占用地址空間。存儲器和I/O地址在地址空間中的安排，用系統(tǒng)存儲映相圖來描述，圖4-5a給出了一例。</p><p>　　設計存儲映相圖是為滿足應用要求，也被硬件設計者用于劃分地址空間以便使系統(tǒng)中存儲設備的地址范圍與存儲映相圖詳細列出的地址相一致。這是由地址譯碼器完成的，如圖4-4所示，用地址總線的地址線作譯

47、碼器的輸入，產(chǎn)生出片選信號，從而成了系統(tǒng)的存儲映相圖。如圖4-5a所示，所考慮的特定系統(tǒng)的RAM從ox1000到ox1FF單元，這是一個地址范圍為4K字節(jié)的存儲器，要求地址總線的低12根地址線A11～A0連接到4K RAM上，剩下的四個高位位址A15～A12被連接到地址譯碼器上，當A15～A12為0001時，譯碼器針對相應的RAM輸出1個片選信號。因此地址譯碼器實現(xiàn)的布爾方程為：</p><p>　　RAM en