外文翻譯--- fpga的安置優(yōu)化方法綜述

1、<p><b>　　附錄A</b></p><p>　　FPGA Placement Optimization Methodology Survey</p><p>　　Sang-Joon Lee and Dr. Kaamran Raahemifar</p><p>　　Department of Electrical and Com

2、puter Engineering Ryerson University</p><p>　　Toronto, ON, Canada</p><p><b>　　ABSTRACT</b></p><p>　　Field Programmable Gate Array (FPGA) is a programmable chip that can

3、be used to quickly implement any digital circuits. Placement is an important part of FPGA design step which determines physical arrangement of the logic blocks in the FPGA. The quality of placement of logic blocks determ

4、ines overall performance of the logic implemented in the FPGA. In this paper, a number of placement optimization techniques are reviewed; min-cut, quadratic, simulated annealing, and a hybrid approach of using g</p>

5、;<p>　　Index Terms Field programmable gate arrays, optimization methods, routing, quadratic programming, simulated annealing, and genetic algorithms</p><p>　　1. INTRODUCTION</p><p>　　Fie

6、ld-Programmable gate arrays (FPGA) are reprogrammable logic chips that can be configured to implement various digital circuits. The Field Programmable Gate Array (FPGA) has gained its popularity in implementing digital c

7、ircuit due to its significant low cost and fast prototyping turn around time. In this survey, an island style FPGA model is considered. Island style FPGA architecture is generally characterized by its two-dimensional sym

8、metry. The generic structure consists of four main elemen</p><p>　　1.1 The Placement Problem</p><p>　　The goal of placement is to find a valid placement for each of configuration logic blocks wh

9、ile trying to minimize the total length of interconnect required. FPGA placement algorithm requires a net-list of logic blocks, which includes</p><p>　　CLBs, I/O pads, and their interconnections. The result

10、of placement is the physical assignment of all blocks and pads on the target FPGA that minimizes one or more objective cost functions. There are three common optimization criteria for placement, time-length driven placem

11、ent, wirelength-driven placement and routability-driven placement. This paper will focus on wire-length placement as the optimization criteria.</p><p>　　1.2 Placement Optimization Techniques</p><p

12、>　　There are five different classes of FPGA placement optimization techniques currently proposed, min-cut, quadratic, simulated annealing, genetic algorithm and particle swarm optimization. In this paper, four techniq

13、ues, min-cut, quadratic, simulated annealing, and a hybrid genetic algorithm with simulated annealing technique will be presented and evaluated. The paper is organized as follows. In section 2, min-cut</p><p&g

14、t;　　placement is presented. In section 3, the quadratic placement technique is presented. In section 4, simulated annealing technique is presented. In section 5, a hybrid</p><p>　　method of using genetic alg

15、orithm and simulated annealing is presented. Lastly, an implementation of hybrid method of genetic algorithm and simulated annealing optimization technique is presented.</p><p>　　2. MIN-CUT PLACEMENT</p&g

16、t;<p>　　The min-cut optimization technique uses recursive partitioning to divide a net-list of circuits into increasingly smaller sub-circuits. The following section describes the</p><p>　　min-cut pla

17、cement approach and evaluation of the placement algorithm.</p><p>　　2.1 Min-Cut Optimization Technique</p><p>　　The min-cut optimization technique recursively apply mincut partitioning to map th

18、e net-list of the circuit into the FPGA layout region. A circuit is recursively bi-partitioned, minimizing the number of cuts of the nets that connect component between partitions, while leaving the highlyconnected block

19、s in one partition. This recursive process is repeated until each partition contains only a few blocks to group the highly-connected blocks together in order to decrease placement cost [3]. Each par</p><p>　

20、　2.2. Pros and Cons</p><p>　　The advantage of min-cut/partition based technique is that it has an open cost function which can be either wire-lengthdriven or time-driven cost function. However, it does not r

21、each global solution. Also, the solution may vary on how the min-cut/partition is performed. As well, as partition is performed, the information from previous step is lost; therefore, the solution may not be able to clim

22、b out of a local minimum.</p><p>　　3. QUADRATIC PLACEMENT</p><p>　　In this section, the quadratic optimization technique implementation for placement problem is reviewed.</p><p>　　3

23、.1. Overview of Quadratic Placement</p><p>　　The quadratic algorithm tries to minimize total squared length by solving linear equation . The cost function is the quadratic sum of the distance from source to

24、destination of each point the path. A cost function for example shown in figure 1 is as follows: This cost function is expanded for entire circuit in the FPGA. The general cost function for quadratic placement is as foll

25、ows:</p><p><b>　?。?）</b></p><p>　　This cost function is expanded for entire circuit in the FPGA.The general cost function for quadratic placement is as follows: <

26、;/p><p>　　Where x and y are the coordinates of a logic of the net-list.Wij is the weight of the edge that connects nodes (xi, yi) and node (xj, yj). Since the input of the quadratic placement is usually represe

27、nted by a hyper-graph, and two nodes can be connected by more than one net, the graph is converted to a weighted hyper-graph, and then two models are used to convert the hyper-graph into a graph .</p><p>　　

28、3.2. Optimization by Quadratic Placement</p><p>　　The following is the quadratic placement optimization technique proposed .</p><p><b>　　Stage 1</b></p><p>　　Build and s

29、olve linear equations.</p><p>　　Map the circuit to the FPGA chip.</p><p>　　Add dummy nodes and expand the placement.</p><p><b>　　Stage 2</b></p><p>　　Refine

30、ment for minimizing linear wire length. Repeat until there is not significant improvement.</p><p>　　Refinement for minimizing linear wire length based on legal placement until there is no significant impro

31、vement.</p><p>　　Re-map the circuit to the FPGA chip.</p><p>　　4. SIMULATED ANNEALING</p><p>　　In this section, first, Simulated annealing algorithm is a universal probability, used

32、 in a large search space to find the optimal solution proposition. Simulated Annealing metallurgy from hardening of the proper nouns.</p><p>　　The principle of simulated annealing and metal annealing is also

33、 similar to the principle: We will apply the theory of thermodynamics to statistical, the search space, think of every point of the air molecules; molecular energy is the kinetic energy of its own; and the search space e

34、very point, but also as the air molecules with the same "energy" to the point of the proposition that the appropriate level.</p><p>　　Algorithm to search for space to an arbitrary starting point: e

35、ach first select a "neighbor", and then calculated from the existing location to "neighbors" of probability. Simulated annealing algorithm can be decomposed into solution space, objective function and

36、 the initial solution of three parts. </p><p>　　Simulated annealing algorithm and the emergence of a new acceptable solution can be divided into the following four steps: The first step is generated by a fun

37、ction from the current solution to produce a solution space is located in the new solution; In order to facilitate the calculation of follow-up and accepted method to reduce time-consuming, usually selected by the curren

38、t after the new solution can transform a simple way to generate new solutions, constitute a new solution if all or part o</p><p>　　The objective function because the only difference arising from the transfor

39、mation part, so the calculation of the objective function worse by incremental calculation of the best. The facts show that for most applications, this is the objective function calculated the quickest way to bad. The th

40、ird step is to determine whether the new solution is accepted, determine a basis for acceptance criteria, the most commonly used criteria of acceptance criteria Metropo1is.The fourth step is to determine </p><

41、p>　　On this basis could be the beginning of the next round of tests. When the new solution was judged to be discarded, then the original basis of the current solution to continue to the next round of tests. Simulated

42、annealing algorithm has nothing to do with the initial value, the algorithm of the solution obtained with the initial solution of the state of S (the starting point is the iterative algorithm) has nothing to do; simulate

43、d annealing algorithm with asymptotic convergence has been proved i</p><p>　　5. HYBRID PLACEMENT: GENETIC ALGORITHM WITH SIMULATED ANNEALING</p><p>　　In this section, detailed information on sim

44、ulated annealing genetic algorithm. Simulated annealing algorithm in the operation of the process of integration into the genetic algorithm, genetic algorithm known as simulated annealing. Simulated annealing algorithm i

45、s based on iterative Monte Carlo method to solve the latter heuristic random search algorithm, which simulated annealing process of solids with the heat balance of random search optimization to achieve the similarity to

46、find the global </p><p>　　5.1. Overview of GASA</p><p>　　As seen in previous section, Simulated Annealing algorithm was described in detail for the placement of the symmetrical FPGA. Genetic alg

47、orithm has advantage of global search over Simulated Annealing because of its robustness of search and problem independence. However, it takes long time to converge in the late phase of the process.</p><p>

48、;　　5.2. Optimization by GASA</p><p>　　In the beginning of the algorithm, the Genetic algorithm(GA) works by using selection, crossover and mutation operators. A significant time is spent in the late phase of

49、 the process of GA in which small improvements are obtained extremely slowly.Simulated annealing (SA) is able to obtain improvements faster than GA in the late phase of the process. Therefore, after a certain numb

50、er of generations, simulated annealing is used to optimize the entire population at a low temperature.</p><p><b>　　附錄B</b></p><p>　　FPGA的安置優(yōu)化方法綜述 </p><p>　　Sang-Joon Lee

51、 和 Dr. Kaamran Raahemifar</p><p>　　電氣與計(jì)算機(jī)工程系 瑞爾森大學(xué) </p><p><b>　　多倫多，加拿大</b></p><p><b>　　摘要</b></p><p>　　現(xiàn)場可編程門陣列( FPGA )是一種可編程的芯片，可用于快速實(shí)施任何數(shù)字電路。

52、在FPGA設(shè)計(jì)步驟中，確定物理安排邏輯模塊占據(jù)著一個(gè)重要組成部分。質(zhì)量安置邏輯塊確定總體業(yè)績的邏輯執(zhí)行的FPGA 。在本文中，將提出一些安置優(yōu)化技術(shù)：分切，二次安置，模擬退火，和一個(gè)利用遺傳算法與模擬退火技術(shù)的混合方法。該方法將對(duì)每一個(gè)優(yōu)化技術(shù)介紹及其優(yōu)點(diǎn)和缺點(diǎn)進(jìn)行評(píng)估?？傮w而言，利用遺傳算法與模擬退火工藝的混合方法能夠生達(dá)到同類型最好成績和全局最優(yōu)解。使用遺傳算法和模擬退火優(yōu)化技術(shù)是實(shí)施利用MATLAB及其結(jié)果使用有線長度驅(qū)動(dòng)安置費(fèi)用

53、的功能。 </p><p>　　索引 現(xiàn)場可編程門陣列，優(yōu)化方法，路由，二次規(guī)劃，模擬退火和遺傳算法</p><p><b>　　1導(dǎo)言 </b></p><p>　　現(xiàn)場可編程門陣列 (FPGA)的編程邏輯芯片，可以被配置為執(zhí)行各種數(shù)字電路?，F(xiàn)場可編程門陣列( FPGA ) 由于其顯著的低成本和快速原型轉(zhuǎn)換，在實(shí)施數(shù)字電路已深受歡迎。在本文中

54、，通過對(duì)一個(gè)FPGA模型考慮。FPGA架構(gòu)，一般特點(diǎn)是雙向?qū)ΨQ。通用結(jié)構(gòu)包括四個(gè)主要部分：配置邏輯塊（CLB），其中通常包含組合或時(shí)序邏輯電路，輸入/輸出模塊（IOB），連接外部設(shè)備的FPGA和可編程互連資源和交換機(jī)。可配置邏輯模塊能夠執(zhí)行多個(gè)邏輯功能。連接塊是通過可編程連接用來連接路由CLB的渠道。同樣，輸入/輸出模塊是通過可編程連接用來連接的縱向和橫向路由的渠道。 </p><p><b>　　1.

55、1安置</b></p><p>　　安置的目標(biāo)是找到一種有效安置的每個(gè)配置邏輯塊試圖盡量減少的總長度互連需要。 FPGA的布局算法需要單獨(dú)的邏輯塊，并通過I /O端口使其互連。由于物理地址是變化的，所有模塊對(duì)目標(biāo)FPGA的最小的一個(gè)或多個(gè)目標(biāo)成本的職能。有三種常見的標(biāo)準(zhǔn)優(yōu)化布局，時(shí)間長度驅(qū)動(dòng)布局，驅(qū)動(dòng)安置和路由驅(qū)動(dòng)的位置。本文將側(cè)重于時(shí)間長度安置作為優(yōu)化標(biāo)準(zhǔn)。</p><p>

56、　　1.2安置優(yōu)化技術(shù) </p><p>　　有5個(gè)不同類別的FPGA布局優(yōu)化技術(shù)，分別為：分切、二次安置、模擬退火、遺傳算法和粒子群優(yōu)化。本文介紹其中四個(gè)技術(shù)，分切，二次安置，模擬退火，模擬退火遺傳算法。本文安排如下：在第2節(jié)中，介紹分切安置技術(shù)；在第3節(jié)中，介紹二次安置技術(shù)；第4節(jié)中，介紹模擬退火技術(shù)；在第5節(jié)中，介紹模擬退火遺傳算法技術(shù)。</p><p><b>　　2 最

57、小切割配置</b></p><p>　　最小切優(yōu)化技術(shù)使用遞歸分割電路來具體分割電路，下面一節(jié)介紹了分切安置方法和布局算法。 </p><p>　　2.1最小切割優(yōu)化技術(shù) </p><p>　　最小切優(yōu)化技術(shù)適用FPGA遞歸分割的地址電路的布局區(qū)域。電路是遞歸雙向分區(qū)，盡量減少網(wǎng)絡(luò)之間連接部分的分割。在同一個(gè)部分區(qū)域，這個(gè)遞歸過程會(huì)反復(fù)進(jìn)行，直至僅包含每

58、個(gè)分區(qū)幾個(gè)高度連接塊組相互結(jié)合，以減少安置費(fèi)用。每個(gè)分區(qū)對(duì)應(yīng)一個(gè)遞歸樹節(jié)點(diǎn)，在第一方式目標(biāo)，分切，使其中一個(gè)部分自行分配，使其削減成為最少的線路。所有邊緣的部分將分區(qū)進(jìn)行加權(quán)，并進(jìn)行計(jì)時(shí)臨界。時(shí)間臨界的邊緣在使用時(shí)間計(jì)算時(shí)間延遲值始終是變化的。此外，它定義了一個(gè)臨界點(diǎn)的最高臨界邊緣的事件。使用時(shí)間臨界邊緣體重標(biāo)準(zhǔn)禁用劃分算法從低到高。因此，在關(guān)鍵時(shí)候，網(wǎng)絡(luò)在同一分區(qū)和電路將保持有一個(gè)較小的時(shí)間延遲。這一進(jìn)程的延遲轉(zhuǎn)讓都是在每一個(gè)分區(qū)的階

59、段。因此，時(shí)機(jī)將更為準(zhǔn)確，每個(gè)階段的時(shí)序驅(qū)動(dòng)分割將更為優(yōu)秀。 </p><p><b>　　2.2 優(yōu)點(diǎn)和缺點(diǎn)</b></p><p>　　最小切割優(yōu)化技術(shù)的優(yōu)點(diǎn)是：它有一個(gè)開放的成本函數(shù)可以是有線或時(shí)間驅(qū)動(dòng)成本函數(shù)。但是，它并沒有達(dá)成全部的解決方法。此外，該解決方案可能會(huì)有所不同的執(zhí)行方法。同時(shí)，作為分區(qū)進(jìn)行，從以前的資料丟失的一步，因此，該解決方案可能無法爬出來當(dāng)

60、地最低限度。 </p><p><b>　　3 二次布局 </b></p><p>　　在這一節(jié)中，將對(duì)二次優(yōu)化技術(shù)實(shí)施安置問題進(jìn)行介紹。 </p><p>　　3.1二次算法概況 </p><p>　　二次算法盡量減少總長度的平方來求解線性方程組?；竞瘮?shù)是二次距離從原點(diǎn)到目的節(jié)點(diǎn)的每一個(gè)點(diǎn)的路徑的總和?；竟δ?，總的

61、成本函數(shù)為二次位置如下：  </p><p><b>　?。?）</b></p><p>　　整個(gè)FPGA電路中，基本函數(shù)擴(kuò)大到一般函數(shù)為二次安置公式如下：</p><p>　　X和Y坐標(biāo)是一個(gè)邏輯連接節(jié)點(diǎn)。由于輸入的二次安置通常是由一個(gè)圖形和兩個(gè)節(jié)點(diǎn)構(gòu)成，因此，通?？梢园岩粋€(gè)以上的網(wǎng)絡(luò)系統(tǒng)或圖表轉(zhuǎn)換為加權(quán)圖形。</p>

62、<p>　　3.2 優(yōu)化二次布局</p><p>　　以下是二次布局優(yōu)化技術(shù)建議：</p><p><b>　　第1階段 </b></p><p>　　建立并求解線性方程組</p><p>　　尋找電路的FPGA芯片。</p><p>　　新增虛擬節(jié)點(diǎn)和擴(kuò)大安置。</p>

63、<p><b>　　第2階段 </b></p><p>　　細(xì)化為盡量減少線性線長。重復(fù)操作直到?jīng)]有明顯的改變。</p><p>　　細(xì)化為盡量減少線性線長度，并根據(jù)公式安置，直到?jīng)]有明顯的改變。 </p><p>　　重新繪制電路的FPGA芯片。 </p><p><b>　　4 模擬退火 <

64、;/b></p><p>　　在本節(jié)中，首先，模擬退火是一種通用概率算法，用來在一個(gè)大的搜尋空間內(nèi)找尋命題的最優(yōu)解。模擬退火來自冶金學(xué)的專有名詞淬火。</p><p>　　模擬退火的原理也和金屬退火的原理近似：我們將熱力學(xué)的理論套用到統(tǒng)計(jì)學(xué)上，將搜尋空間內(nèi)每一點(diǎn)想像成空氣內(nèi)的分子；分子的能量，就是它本身的動(dòng)能；而搜尋空間內(nèi)的每一點(diǎn)，也像空氣分子一樣帶有“能量”，以表示該點(diǎn)對(duì)命題的合適

65、程度。算法先以搜尋空間內(nèi)一個(gè)任意點(diǎn)作起始：每一部先選擇一個(gè)“鄰居”，然后再計(jì)算從現(xiàn)有位置到達(dá)“鄰居”的概率。</p><p>　　模擬退火算法可以分解為解空間、目標(biāo)函數(shù)和初始解三部分。</p><p>　　模擬退火算法新解的產(chǎn)生和接受可分為如下四個(gè)步驟： </p><p>　　第一步是由一個(gè)產(chǎn)生函數(shù)從當(dāng)前解產(chǎn)生一個(gè)位于解空間的新解；為便于后續(xù)的計(jì)算和接受，減少算法耗

66、時(shí)，通常選擇由當(dāng)前新解經(jīng)過簡單地變換即可產(chǎn)生新解的方法，如對(duì)構(gòu)成新解的全部或部分元素進(jìn)行置換、互換等，注意到產(chǎn)生新解的變換方法決定了當(dāng)前新解的鄰域結(jié)構(gòu)，因而對(duì)冷卻進(jìn)度表的選取有一定的影響。 </p><p>　　第二步是計(jì)算與新解所對(duì)應(yīng)的目標(biāo)函數(shù)差。因?yàn)槟繕?biāo)函數(shù)差僅由變換部分產(chǎn)生，所以目標(biāo)函數(shù)差的計(jì)算最好按增量計(jì)算。事實(shí)表明，對(duì)大多數(shù)應(yīng)用而言，這是計(jì)算目標(biāo)函數(shù)差的最快方法。 </p><p&g

67、t;　　第三步是判斷新解是否被接受,判斷的依據(jù)是一個(gè)接受準(zhǔn)則，最常用的接受準(zhǔn)則是Metropo1is準(zhǔn)則。 </p><p>　　第四步是當(dāng)新解被確定接受時(shí)，用新解代替當(dāng)前解，這只需將當(dāng)前解中對(duì)應(yīng)于產(chǎn)生新解時(shí)的變換部分予以實(shí)現(xiàn)，同時(shí)修正目標(biāo)函數(shù)值即可。此時(shí)，當(dāng)前解實(shí)現(xiàn)了一次迭代?？稍诖嘶A(chǔ)上開始下一輪試驗(yàn)。而當(dāng)新解被判定為舍棄時(shí)，則在原當(dāng)前解的基礎(chǔ)上繼續(xù)下一輪試驗(yàn)。 </p><p>　　

68、模擬退火算法與初始值無關(guān)，算法求得的解與初始解狀態(tài)S(是算法迭代的起點(diǎn))無關(guān)；模擬退火算法具有漸近收斂性，已在理論上被證明是一種以概率l 收斂于全局最優(yōu)解的全局優(yōu)化算法；模擬退火算法具有并行性。</p><p>　　5 混合配置：模擬退火遺傳算法</p><p>　　在本節(jié)中，詳細(xì)介紹了模擬退火遺傳算法。在模擬退火算法的運(yùn)行過程中溶入遺傳算法，稱為模擬退火遺傳算法。模擬退火算法是基于Mon

69、te Carlo迭代求解法后種啟發(fā)式隨機(jī)搜索算法，它模擬固體物質(zhì)退火過程的熱平衡問題與隨機(jī)搜索尋優(yōu)問題的相似性來達(dá)到尋找全局最優(yōu)或近似全局最優(yōu)的目的。在搜索最優(yōu)解的過程中，模擬退火法除了可以接受優(yōu)化解外，還有一個(gè)隨機(jī)接受準(zhǔn)則（Metropolis準(zhǔn)則）有限度地接受惡化解，并且接受惡化解的概率慢慢趨向于0，這使得算法有可能從局部極值區(qū)域中跳出，即可能找到全局最優(yōu)解，并保證了算法的收斂性?；旌系倪z傳算法和模擬退火（ GASA ）優(yōu)化技術(shù)用于

70、安置對(duì)稱的FPGA 。該算法包括兩個(gè)階段。首先，它利用遺傳算法優(yōu)化安置在全球范圍內(nèi)，然后模擬退火算法用于改善解決混合安置辦法是建議使用的優(yōu)勢(shì)，尋求全局最優(yōu)解的遺傳算法收斂速度慢克服遺傳算法在后期階段的過程中使用低溫模擬退火算法。</p><p>　　5.1 GASA概況</p><p>　　正如上一節(jié)所述，模擬退火算法能夠詳細(xì)描述對(duì)稱的FPGA地址 。遺傳算法模擬退火由于其穩(wěn)定的搜索和問題

71、的獨(dú)立性已經(jīng)被廣為采用。然而，它需要很長時(shí)間才能達(dá)到后期的進(jìn)程階段。</p><p>　　5.2 GASA的優(yōu)化 </p><p>　　在最初的算法里，遺傳算法（ GA ）的工作原理是利用選擇，交叉來變換算法。大部分的時(shí)間都會(huì)花在后期進(jìn)程階段，其中一些小的改進(jìn)，得到了極為顯著的效果。退火（ SA ）是能夠獲得后期階段的進(jìn)程改進(jìn)遺傳算法的速度比。因此，在一定的算法里，是通過模擬退火來優(yōu)化低溫