單片機(jī)應(yīng)用的外文翻譯

1、<p>　　單片機(jī)應(yīng)用的外文資料</p><p><b>　　主要性能</b></p><p>　　? 與MCS-51單片機(jī)產(chǎn)品兼容</p><p>　　? 8K字節(jié)在系統(tǒng)可編程Flash存儲(chǔ)器</p><p>　　? 1000次擦寫周期</p><p>　　? 全靜態(tài)操作：0Hz～33

2、Hz</p><p>　　? 三級(jí)加密程序存儲(chǔ)器</p><p>　　? 32個(gè)可編程I/O口線</p><p>　　? 三個(gè)16位定時(shí)器/計(jì)數(shù)器</p><p><b>　　? 八個(gè)中斷源</b></p><p>　　? 全雙工UART串行通道</p><p>　　? 低

3、功耗空閑和掉電模式</p><p>　　? 掉電后中斷可喚醒</p><p><b>　　? 看門狗定時(shí)器</b></p><p><b>　　? 雙數(shù)據(jù)指針</b></p><p><b>　　? 掉電標(biāo)識(shí)符</b></p><p><b>

4、　　1.功能特征描述</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K 在系統(tǒng)可編程Flash 存儲(chǔ)器。使用Atmel 公司高密度非易失性存儲(chǔ)器技術(shù)制造，與工業(yè)80C51 產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲(chǔ)器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8 位CPU 和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應(yīng)用系統(tǒng)

5、提供高靈活、超有效的解決方案。AT89S52具有以下標(biāo)準(zhǔn)功能： 8k字節(jié)Flash，256字節(jié)RAM，32 位I/O 口線，看門狗定時(shí)器，2 個(gè)數(shù)據(jù)指針，三個(gè)16 位定時(shí)器/計(jì)數(shù)器，一個(gè)6向量2級(jí)中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時(shí)鐘電路。另外，AT89S52 可降至0Hz 靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式。空閑模式下，CPU停止工作，允許RAM、定時(shí)器/計(jì)數(shù)器、串口、中斷繼續(xù)工作。掉電保護(hù)方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)

6、，單片機(jī)一切工作停止，直到下一個(gè)中斷或硬件復(fù)位為止。</p><p><b>　　2.引腳功能</b></p><p><b>　　VCC ：電源</b></p><p><b>　　GND: 接地</b></p><p>　　P0口： P0口是一個(gè)8位漏極開(kāi)路的雙向I/O口。

7、作為輸出口，每位能驅(qū)動(dòng)8個(gè)TTL邏輯電平。對(duì)P0端口寫“1”時(shí)，引腳用作高阻抗輸入。當(dāng)訪問(wèn)外部程序和數(shù)據(jù)存儲(chǔ)器時(shí)，P0口也被作為低8位地址/數(shù)據(jù)復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻。在flash編程時(shí)，P0口也用來(lái)接收指令字節(jié)；在程序校驗(yàn)時(shí)，輸出指令字節(jié)。程序校驗(yàn)時(shí)，需要外部上拉電阻。</p><p>　　P1口：P1 口是一個(gè)具有內(nèi)部上拉電阻的8 位雙向I/O 口，p1 輸出緩沖器能驅(qū)動(dòng)4 個(gè)TTL 邏輯電

8、平。對(duì)P1 端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時(shí)器/計(jì)數(shù)器2的外部計(jì)數(shù)輸入（P1.0/T2）和時(shí)器/計(jì)數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。在flash編程和校驗(yàn)時(shí)，P1口接收低8位地址字節(jié)。</p><p><b>　　表1</b><

9、;/p><p>　　P2口：P2 口是一個(gè)具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2 輸出緩沖器能驅(qū)動(dòng)4 個(gè)TTL 邏輯電平。對(duì)P2 端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電（IIL）。在訪問(wèn)外部程序存儲(chǔ)器或用16位地址讀取外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX @DPTR）時(shí)，P2 口送出高八位地址。在這種應(yīng)用中，P2 口使用很強(qiáng)的內(nèi)部

10、上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口輸出P2鎖存器的內(nèi)容。在flash編程和校驗(yàn)時(shí)，P2口也接收高8位地址字節(jié)和一些控制信號(hào)。</p><p>　　P3口：P3 口是一個(gè)有內(nèi)部上拉電阻的8 位雙向I/O 口，p2 輸出緩沖器能驅(qū)動(dòng)4 個(gè)TTL 邏輯電平。對(duì)P3 端口寫“1”時(shí)，內(nèi)部上拉電阻把端口拉高，此時(shí)可以作為輸入口使用。作為輸入使用時(shí)，被外部拉低的引腳由于內(nèi)部電阻的原因

11、，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗(yàn)時(shí)，P3口也接收一些控制信號(hào)。</p><p><b>　　表2</b></p><p>　　RST：復(fù)位輸入。晶振工作時(shí)，RST腳持續(xù)2 個(gè)機(jī)器周期高電平將使單片機(jī)復(fù)位?？撮T狗計(jì)時(shí)完成后，RST 腳輸出96 個(gè)晶振周期的高電平。特殊寄存器AUXR(地址8EH

12、)上的DISRTO位可以使此功能無(wú)效。DISRTO默認(rèn)狀態(tài)下，復(fù)位高電平有效。</p><p>　　ALE/：地址鎖存控制信號(hào)（ALE）是訪問(wèn)外部程序存儲(chǔ)器時(shí)，鎖存低8 位地址的輸出脈沖。在flash編程時(shí)，此引腳()也用作編程輸入脈沖。在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來(lái)作為外部定時(shí)器或時(shí)鐘使用。然而，特別強(qiáng)調(diào)，在每次訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，ALE脈沖將會(huì)跳過(guò)。如果需要，通過(guò)將地址為8E

13、H的SFR的第0位置 “1”，ALE操作將無(wú)效。這一位置 “1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時(shí)有效。否則，ALE 將被微弱拉高。這個(gè)ALE 使能標(biāo)志位（地址為8EH的SFR的第0位）的設(shè)置對(duì)微控制器處于外部執(zhí)行模式下無(wú)效。</p><p>　?。和獠砍绦虼鎯?chǔ)器選通信號(hào)()是外部程序存儲(chǔ)器選通信號(hào)。當(dāng)AT89S52從外部程序存儲(chǔ)器執(zhí)行外部代碼時(shí)，在每個(gè)機(jī)器周期被激活兩次，而在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，將不

14、被激活。</p><p>　　/VPP：訪問(wèn)外部程序存儲(chǔ)器控制信號(hào)。為使能從0000H 到FFFFH的外部程序存儲(chǔ)器讀取指令，必須接GND。為了執(zhí)行內(nèi)部程序指令，應(yīng)該接VCC。在flash編程期間，也接收12伏VPP電壓。</p><p>　　XTAL1：振蕩器反相放大器和內(nèi)部時(shí)鐘發(fā)生電路的輸入端。</p><p>　　XTAL2：振蕩器反相放大器的輸出端。<

15、/p><p><b>　　3.存儲(chǔ)器結(jié)構(gòu)</b></p><p>　　MCS-51器件有單獨(dú)的程序存儲(chǔ)器和數(shù)據(jù)存儲(chǔ)器。外部程序存儲(chǔ)器和數(shù)據(jù)存儲(chǔ)器都可以64K尋址。</p><p><b>　　3.1程序存儲(chǔ)器</b></p><p>　　如果引腳接地，程序讀取只從外部存儲(chǔ)器開(kāi)始。對(duì)于89S52，如果 接

16、VCC，程序讀寫先從內(nèi)部存儲(chǔ)器（地址為0000H～1FFFH）開(kāi)始，接著從外部尋址，尋址地址為：2000H~FFFFH。</p><p><b>　　3.2數(shù)據(jù)存儲(chǔ)器</b></p><p>　　AT89S52 有256 字節(jié)片內(nèi)數(shù)據(jù)存儲(chǔ)器。高128 字節(jié)與特殊功能寄存器重疊。也就是說(shuō)高128字節(jié)與特殊功能寄存器有相同的地址，而物理上是分開(kāi)的。當(dāng)一條指令訪問(wèn)高于7FH

17、 的地址時(shí)，尋址方式?jīng)Q定CPU 訪問(wèn)高128 字節(jié)RAM 還是特殊功能寄存器空間。直接尋址方式訪問(wèn)特殊功能寄存器（SFR）。例如，下面的直接尋址指令訪問(wèn)0A0H（P2口）存儲(chǔ)單元</p><p>　　MOV 0A0H , #data</p><p>　　使用間接尋址方式訪問(wèn)高128 字節(jié)RAM。例如，下面的間接尋址方式中，R0 內(nèi)容為0A0H，訪問(wèn)的是地址0A0H的寄存器，而不是P2口（它

18、的地址也是0A0H）。</p><p>　　MOV @R0 , #data</p><p>　　堆棧操作也是簡(jiǎn)介尋址方式。因此，高128字節(jié)數(shù)據(jù)RAM也可用于堆棧空間。</p><p><b>　　4.看門狗定時(shí)器</b></p><p>　　WDT是一種需要軟件控制的復(fù)位方式。WDT 由13位計(jì)數(shù)器和特殊功能寄存器中的

19、看門狗定時(shí)器復(fù)位存儲(chǔ)器（WDTRST）構(gòu)成。WDT 在默認(rèn)情況下無(wú)法工作；為了激活WDT，戶用必須往WDTRST 寄存器（地址：0A6H）中依次寫入01EH 和0E1H。當(dāng)WDT激活后，晶振工作，WDT在每個(gè)機(jī)器周期都會(huì)增加。WDT計(jì)時(shí)周期依賴于外部時(shí)鐘頻率。除了復(fù)位（硬件復(fù)位或WDT溢出復(fù)位），沒(méi)有辦法停止WDT工作。當(dāng)WDT溢出，它將驅(qū)動(dòng)RSR引腳一個(gè)高個(gè)電平輸出。</p><p><b>　　4.

20、1WDT的使用</b></p><p>　　為了激活WDT，用戶必須向WDTRST寄存器（地址為0A6H的SFR）依次寫入0E1H和0E1H。當(dāng)WDT激活后，用戶必須向WDTRST寫入01EH和0E1H喂狗來(lái)避免WDT溢出。當(dāng)計(jì)數(shù)達(dá)到8191(1FFFH)時(shí)，13 位計(jì)數(shù)器將會(huì)溢出，這將會(huì)復(fù)位器件。晶振正常工作、WDT激活后，每一個(gè)機(jī)器周期WDT 都會(huì)增加。為了復(fù)位WDT，用戶必須向WDTRST 寫入

21、01EH 和0E1H（WDTRST 是只讀寄存器）。WDT 計(jì)數(shù)器不能讀或?qū)?。?dāng)WDT 計(jì)數(shù)器溢出時(shí)，將給RST 引腳產(chǎn)生一個(gè)復(fù)位脈沖輸出，這個(gè)復(fù)位脈沖持續(xù)96個(gè)晶振周期（TOSC），其中TOSC=1/FOSC。為了很好地使用WDT，應(yīng)該在一定時(shí)間內(nèi)周期性寫入那部分代碼，以避免WDT復(fù)位。</p><p>　　4.2掉電和空閑方式下的WDT</p><p>　　在掉電模式下，晶振停止工作，

22、這意味這WDT也停止了工作。在這種方式下，用戶不必喂狗。有兩種方式可以離開(kāi)掉電模式：硬件復(fù)位或通過(guò)一個(gè)激活的外部中斷。通過(guò)硬件復(fù)位退出掉電模式后，用戶就應(yīng)該給WDT 喂狗，就如同通常AT89S52 復(fù)位一樣。通過(guò)中斷退出掉電模式的情形有很大的不同。中斷應(yīng)持續(xù)拉低很長(zhǎng)一段時(shí)間，使得晶振穩(wěn)定。當(dāng)中斷拉高后，執(zhí)行中斷服務(wù)程序。為了防止WDT在中斷保持低電平的時(shí)候復(fù)位器件，WDT 直到中斷拉低后才開(kāi)始工作。這就意味著WDT 應(yīng)該在中斷服務(wù)程序中

23、復(fù)位。為了確保在離開(kāi)掉電模式最初的幾個(gè)狀態(tài)WDT不被溢出，最好在進(jìn)入掉電模式前就復(fù)WDT。在進(jìn)入待機(jī)模式前，特殊寄存器AUXR的WDIDLE位用來(lái)決定WDT是否繼續(xù)計(jì)數(shù)。默認(rèn)狀態(tài)下，在待機(jī)模式下，WDIDLE＝0，WDT繼續(xù)計(jì)數(shù)。為了防止WDT在待機(jī)模式下復(fù)位AT89S52，用戶應(yīng)該建立一個(gè)定時(shí)器，定時(shí)離開(kāi)待機(jī)模式，喂狗，再重新進(jìn)入待機(jī)模式。</p><p><b>　　5.UART</b>

24、</p><p>　　在AT89S52 中，UART 的操作與AT89C51 和AT89C52 一樣。為了獲得更深入的關(guān)于UART 的信息，可參考ATMEL 網(wǎng)站（http//www.atmel.com）。從這個(gè)主頁(yè)，選擇“Products”，然后選擇“8051-Architech Flash Microcontroller”，再選擇“ProductOverview”即可。</p><p>

25、;　　6.定時(shí)器0 和定時(shí)器1</p><p>　　在AT89S52 中，定時(shí)器0 和定時(shí)器1 的操作與AT89C51 和AT89C52 一樣。為了獲得更深入的關(guān)于UART 的信息，可參考ATMEL 網(wǎng)站（http://www.atmel.com）。從這個(gè)主頁(yè)，選擇“Products”，然后選擇“8051-Architech Flash Microcontroller”，再選擇“Product Overview”

26、即可。</p><p><b>　　7.定時(shí)器2</b></p><p>　　定時(shí)器2是一個(gè)16位定時(shí)/計(jì)數(shù)器，它既可以做定時(shí)器，又可以做事件計(jì)數(shù)器。其工作方式由特殊寄存器T2CON中的C/T2位選擇（如表2所示）。定時(shí)器2有三種工作模式：捕捉方式、自動(dòng)重載（向下或向上計(jì)數(shù)）和波特率發(fā)生器。如表3 所示，工作模式由T2CON中的相關(guān)位選擇。定時(shí)器2 有2 個(gè)8位寄存器

27、：TH2和TL2。在定時(shí)工作方式中，每個(gè)機(jī)器周期，TL2 寄存器都會(huì)加1。由于一個(gè)機(jī)器周期由12 個(gè)晶振周期構(gòu)成，因此，計(jì)數(shù)頻率就是晶振頻率的1/12。</p><p>　　表3 定時(shí)器2工作模式</p><p>　　在計(jì)數(shù)工作方式下，寄存器在相關(guān)外部輸入角T2 發(fā)生1 至0 的下降沿時(shí)增加1。在這種方式下，每個(gè)機(jī)器周期的S5P2期間采樣外部輸入。一個(gè)機(jī)器周期采樣到高電平，而下一個(gè)周期采樣

28、到低電平，計(jì)數(shù)器將加1。在檢測(cè)到跳變的這個(gè)周期的S3P1 期間，新的計(jì)數(shù)值出現(xiàn)在寄存器中。因?yàn)樽R(shí)別1－0的跳變需要2個(gè)機(jī)器周期（24個(gè)晶振周期），所以，最大的計(jì)數(shù)頻率不高于晶振頻率的1/24。為了確保給定的電平在改變前采樣到一次，電平應(yīng)該至少在一個(gè)完整的機(jī)器周期內(nèi)保持不變。</p><p><b>　　7.1捕捉方式</b></p><p>　　在捕捉模式下，通過(guò)T2

29、CON中的EXEN2來(lái)選擇兩種方式。如果EXEN2=0，定時(shí)器2時(shí)一個(gè)16位定時(shí)/計(jì)數(shù)器，溢出時(shí)，對(duì)T2CON 的TF2標(biāo)志置位，TF2引起中斷。如果EXEN2=1，定時(shí)器2做相同的操作。除上述功能外，外部輸入T2EX引腳（P1.1）1至0的下跳變也會(huì)使得TH2和TL2中的值分別捕捉到RCAP2H和RCAP2L中。除此之外，T2EX 的跳變會(huì)引起T2CON 中的EXF2 置位。像TF2 一樣，T2EX 也會(huì)引起中斷。</p>

30、<p><b>　　7.2自動(dòng)重載</b></p><p>　　當(dāng)定時(shí)器2 工作于16 位自動(dòng)重載模式，可對(duì)其編程實(shí)現(xiàn)向上計(jì)數(shù)或向下計(jì)數(shù)。這一功能可以通過(guò)特殊寄存器T2MOD（見(jiàn)表4）中的DCEN（向下計(jì)數(shù)允許位）來(lái)實(shí)現(xiàn)。通過(guò)復(fù)位，DCEN 被置為0，因此，定時(shí)器2 默認(rèn)為向上計(jì)數(shù)。DCEN 設(shè)置后，定時(shí)器2就可以取決于T2EX向上、向下計(jì)數(shù)。DCEN=0 時(shí)，定時(shí)器2 自動(dòng)計(jì)

31、數(shù)。通過(guò)T2CON 中的EXEN2 位可以選擇兩種方式。如果EXEN2=0，定時(shí)器2計(jì)數(shù)，計(jì)到0FFFFH后置位TF2溢出標(biāo)志。計(jì)數(shù)溢出也使得定時(shí)器寄存器重新從RCAP2H 和RCAP2L 中加載16 位值。定時(shí)器工作于捕捉模式，RCAP2H和RCAP2L的值可以由軟件預(yù)設(shè)。如果EXEN2=1，計(jì)數(shù)溢出或在外部T2EX（P1.1）引腳上的1到0的下跳變都會(huì)觸發(fā)16位重載。這個(gè)跳變也置位EXF2中斷標(biāo)志位。置位DCEN，允許定時(shí)器2向上或

32、向下計(jì)數(shù)。在這種模式下，T2EX引腳控制著計(jì)數(shù)的方向。T2EX上的一個(gè)邏輯1使得定時(shí)器2向上計(jì)數(shù)。定時(shí)器計(jì)到0FFFFH溢出，并置位TF2。定時(shí)器的溢出也使得RCAP2H和RCAP2L中的16位值分別加載到定時(shí)器存儲(chǔ)器TH2和TL2中。T2EX</p><p><b>　　8.波特率發(fā)生器</b></p><p>　　通過(guò)設(shè)置T2CON中的TCLK或RCLK可選擇定時(shí)

33、器2 作為波特率發(fā)生器。如果定時(shí)器2作為發(fā)送或接收波特率發(fā)生器，定時(shí)器1可用作它用，發(fā)送和接收的波特率可以不同。如圖8 所示，設(shè)置RCLK 和（或）TCLK 可以使定時(shí)器2 工作于波特率產(chǎn)生模式。波特率產(chǎn)生工作模式與自動(dòng)重載模式相似，因此，TH2 的翻轉(zhuǎn)使得定時(shí)器2 寄存器重載被軟件預(yù)置16位值的RCAP2H和RCAP2L中的值。模式1和模式3的波特率由定時(shí)器2溢出速率決定，具體如下公式：</p><p>　　定

34、時(shí)器可設(shè)置成定時(shí)器，也可為計(jì)數(shù)器。在多數(shù)應(yīng)用情況下，一般配置成定時(shí)方式（CP/=0）。定時(shí)器2 用于定時(shí)器操作與波特率發(fā)生器有所不同，它在每一機(jī)器周（1/12晶振周期）都會(huì)增加；然而，作為波特率發(fā)生器，它在每一機(jī)器狀態(tài)（1/2晶振周期）都會(huì)增加。波特率計(jì)算公式如下：</p><p>　　其中，（RCAP2H,RCAP2L）是RCAP2H和RCAP2L組成的16位無(wú)符號(hào)整數(shù)。特別強(qiáng)調(diào)，TH2的翻轉(zhuǎn)并不置位TF2，也

35、不產(chǎn)生中斷； EXEN2置位后，T2EX引腳上1～0的下跳變不會(huì)使（RCAP2H，RCAP2L）重載到（TH2，TL2）中。因此，定時(shí)器2作為波特率發(fā)生器，T2EX也還可以作為一個(gè)額外的外部中斷。定時(shí)器2處于波特率產(chǎn)生模式，TR2=1，定時(shí)器2正常工作。TH2或TL2不應(yīng)該讀寫。在這種模式下，定時(shí)器在每一狀態(tài)都會(huì)增加，讀或?qū)懢筒粫?huì)準(zhǔn)確。寄存器RCAP2可以讀，但不能寫，因?yàn)閷懣赡芎椭剌d交迭，造成寫和重載錯(cuò)誤。在讀寫定時(shí)器2 或RCAP2

36、寄存器時(shí)，應(yīng)該關(guān)閉定時(shí)器（TR2清0）。</p><p><b>　　9.可編程時(shí)鐘輸出</b></p><p>　　可以通過(guò)編程在P1.0 引腳輸出一個(gè)占空比為50%的時(shí)鐘信號(hào)。這個(gè)引腳除了常規(guī)的I/O 角外，還有兩種可選擇功能。它可以通過(guò)編程作為定時(shí)器/計(jì)數(shù)器2 的外部時(shí)鐘輸入或占空比為50%的時(shí)鐘輸出。當(dāng)工作頻率為16MHZ時(shí)，時(shí)鐘輸出頻率范圍為61HZ到4HZ

37、。為了把定時(shí)器2配置成時(shí)鐘發(fā)生器，位C/（T2CON.1）必須清0，位T2OE（T2MOD.1）必須置1。位TR2（T2CON.2）啟動(dòng)、停止定時(shí)器。時(shí)鐘輸出頻率取決于晶振頻率和定時(shí)器2捕捉寄存器（RCAP2H，RCAP2L）的重載值，如公式所示：</p><p>　　在時(shí)鐘輸出模式下，定時(shí)器2不會(huì)產(chǎn)生中斷，這和定時(shí)器2用作波特率發(fā)生器一樣。定時(shí)器2也可以同時(shí)用作波特率發(fā)生器和時(shí)鐘產(chǎn)生。不過(guò)，波特率和輸出時(shí)鐘頻率

38、相互并不獨(dú)立，它們都依賴于RCAP2H和RCAP2L。</p><p><b>　　10.中斷</b></p><p>　　AT89S52 有6個(gè)中斷源：兩個(gè)外部中斷（ 和），三個(gè)定時(shí)中斷（定時(shí)器0、1、2）和一個(gè)串行中斷。每個(gè)中斷源都可以通過(guò)置位或清除特殊寄存器IE 中的相關(guān)中斷允許控制位分別使得中斷源有效或無(wú)效。IE還包括一個(gè)中斷允許總控制位EA，它能一次禁止所有

39、中斷。IE.6位是不可用的。對(duì)于AT89S52，IE.5位也是不能用的。用戶軟件不應(yīng)給這些位寫1。它們?yōu)锳T89系列新產(chǎn)品預(yù)留。定時(shí)器2可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。程序進(jìn)入中斷服務(wù)后，這些標(biāo)志位都可以由硬件清0。實(shí)際上，中斷服務(wù)程序必須判定是否是TF2 或EXF2激活中斷，標(biāo)志位也必須由軟件清0。定時(shí)器0和定時(shí)器1標(biāo)志位TF0 和TF1在計(jì)數(shù)溢出的那個(gè)周期的S5P2被置位。它們的值一直到下一個(gè)周期被電路捕捉下

40、來(lái)。然而，定時(shí)器2 的標(biāo)志位TF2 在計(jì)數(shù)溢出的那個(gè)周期的S2P2被置位，在同一個(gè)周期被電路捕捉下來(lái)。</p><p><b>　　11.晶振特性</b></p><p>　　AT89S52 單片機(jī)有一個(gè)用于構(gòu)成內(nèi)部振蕩器的反相放大器，XTAL1 和XTAL2 分別是放大器的輸入、輸出端。石英晶體和陶瓷諧振器都可以用來(lái)一起構(gòu)成自激振蕩器。從外部時(shí)鐘源驅(qū)動(dòng)器件的話，XT

41、AL2 可以不接，而從XTAL1 接入。由于外部時(shí)鐘信號(hào)經(jīng)過(guò)二分頻觸發(fā)后作為外部時(shí)鐘電路輸入的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒(méi)有其它要求，最長(zhǎng)低電平持續(xù)時(shí)間和最少高電平持續(xù)時(shí)間等還是要符合要求的。</p><p><b>　　12.空閑模式</b></p><p>　　在空閑工作模式下，CPU 處于睡眠狀態(tài)，而所有片上外部設(shè)備保持激活狀態(tài)。這種狀態(tài)可以通過(guò)軟件產(chǎn)生。在這

42、種狀態(tài)下，片上RAM和特殊功能寄存器的內(nèi)容保持不變?？臻e模式可以被任一個(gè)中斷或硬件復(fù)位終止。由硬件復(fù)位終止空閑模式只需兩個(gè)機(jī)器周期有效復(fù)位信號(hào)，在這種情況下，片上硬件禁止訪問(wèn)內(nèi)部RAM，而可以訪問(wèn)端口引腳?？臻e模式被硬件復(fù)位終止后，為了防止預(yù)想不到的寫端口，激活空閑模式的那一條指令的下一條指令不應(yīng)該是寫端口或外部存儲(chǔ)器。</p><p><b>　　13.掉電模式</b></p>

43、<p>　　在掉電模式下，晶振停止工作，激活掉電模式的指令是最后一條執(zhí)行指令。片上RAM和特殊功能寄存器保持原值，直到掉電模式終止。掉電模式可以通過(guò)硬件復(fù)位和外部中斷退出。復(fù)位重新定義了SFR 的值，但不改變片上RAM 的值。在VCC未恢復(fù)到正常工作電壓時(shí)，硬件復(fù)位不能無(wú)效，并且應(yīng)保持足夠長(zhǎng)的時(shí)間以使晶振重新工作和初始化。</p><p><b>　　AT89S52</b>&l

44、t;/p><p><b>　　Features</b></p><p>　　? Compatible with MCS-51 Products</p><p>　　? 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 10,000 Write/Erase Cycle

45、s</p><p>　　? 4.0V to 5.5V Operating Range</p><p>　　? Fully Static Operation: 0 Hz to 33 MHz</p><p>　　? Three-level Program Memory Lock </p><p>　　? 256 x 8-bit Internal

46、RAM </p><p>　　? 32 Programmable I/O Lines </p><p>　　? Three 16-bit Timer/Counters </p><p>　　? Eight Interrupt Sources</p><p>　　? Full Duplex UART Serial Channel </p&

47、gt;<p>　　? Low-power Idle and Power-down Modes</p><p>　　? Interrupt Recovery from Power-down Mode </p><p>　　? Watchdog Timer ? Dual Data Pointer </p><p>　　? Power-off Flag ?

48、Fast Programming Time </p><p>　　? Flexible ISP Programming (Byte and Page Mode) </p><p>　　? Green (Pb/Halide-free) Packaging Option</p><p>　　1.Description</p><p>　　The

49、AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compati

50、ble with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-b

51、it CPU with in-system programmable Flash on a monolithic</p><p>　　The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, t

52、hree 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to

53、zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,</p><p>　　2.Pin Description</p><p>　　VCC ：Supply voltag

54、e.</p><p>　　GND ：Ground.</p><p>　　Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins

55、 can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 al

56、so receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pu</p><p>　　Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The

57、Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled

58、 low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger inpu</p><p

59、>　　Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p><b>　　Table1</b></p><p>　　Port 2：Port 2 is an 8-bit bidirectional I/O port wit

60、h internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that ar

61、e externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory

62、that use</p><p>　　Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high

63、by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programmi

64、ng and verification. Port 3 also serves the functions of various special features of the AT</p><p><b>　　Table2</b></p><p>　　RST：Reset input. A high on this pin for two machine cycles

65、 while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the defaul

66、t state of bit DISRTO, the RESET HIGH out feature is enabled.</p><p>　　ALE/：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin

67、 is also the program pulse input () during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however

68、, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR l</p><p>　?。篜rogram Store Enable () is the read strobe to extern

69、al program memory. When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to exter-nal data memory.</p>

70、<p>　　/VPP：External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is pro

71、grammed, will be internally latched on reset. should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.</p><p>

72、;　　XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　XTAL2：Output from the inverting oscillator amplifier.</p><p>　　3.Memory Organizat

73、ion</p><p>　　MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.</p><p>　　3.1 Program Memory</

74、p><p>　　If the pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal m

75、emory and fetches to addresses 2000H through FFFFH are to external memory.</p><p>　　3.2 Data Memory</p><p>　　The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a paralle

76、l address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal locatio

77、n above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the S</p><p>　　MO

78、V 0A0H, #data</p><p>　　Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte

79、at address 0A0H, rather than P2 (whose address is 0A0H).</p><p>　　MOV @R0, #data</p><p>　　Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are a

80、vailable as stack space.</p><p>　　4.Watchdog Timer (One-time Enabled with Reset-out)</p><p>　　The WDT is intended as a recovery method in situations where the CPU may be subjected to software up

81、sets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST regis

82、ter (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock f</p><p>　　4.1 Using the WDT

83、</p><p>　　To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST t

84、o avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This mea

85、ns the user must reset the WDT at least every 16383 machine cycles. To reset the WD</p><p>　　4.2 WDT During Power-down and Idle</p><p>　　In Power-down mode the oscillator stops, which means the

86、WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prio

87、r to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly differ

88、ent</p><p><b>　　5. UART</b></p><p>　　The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, please click

89、 on the document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF</p><p>　　6. Timer 0 and 1</p><p>　　Timer 0 and Timer 1 in the AT89S52 operate the

90、 same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_docume

91、nts/DOC4316.PDF</p><p>　　7. Timer 2</p><p>　　Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/ in the SFR T2C

92、ON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and

93、 TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator pe</p><p>　　Table3 Timer 2 Operating Modes</p><p>　　In the Count

94、er function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the sampl

95、es show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two ma

96、chine cycles (24 oscillator periods) are require</p><p>　　7.1 Capture Mode</p><p>　　In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer o

97、r counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-tion at external input T2EX also causes the

98、current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, li</p><p>　　7.2 Auto-reload (Up or Down

99、 Counter)</p><p>　　Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD . Upon

100、reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN = 0. In this m

101、ode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFF</p><p>　　8. Baud Rate Generator</p><p>　　Timer 2 is selected as the baud rate generator by setting TC

102、LK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Tim

103、er 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and