外文翻譯----時鐘精度要求確定為uart的通訊

1、<p><b>　　科技文章摘譯 </b></p><p><b>　　英文原文 </b></p><p>　　Abstract: This application note discusses the timing requirements for the commonly used serial asynchronous commu

2、nications protocol implemented in UARTs, and shows how to determine the tolerance for the UART clock source at both ends of an asynchronous link.</p><p>　　Background</p><p>　　The RS-232 specifi

3、cation dates back to 1962, when it was first released by the EIA (Electronic Industries Association). The specification has changed over time, incorporating higher data rates and closing the compatibility gaps between TI

4、A (Telecommunication Industry Association) and international (ITU, ISO) standards. The current version of the RS-232 specification is EIA/TIA-232-F, dated October 1997. </p><p>　　The protocol benefited from

5、the availability of MSI ICs from the late 1970s which had the complexity to handle the standard at reasonable cost. These ICs are generically called UARTs (Universal Asynchronous Receive Transmit). Many LSI ICs (includin

6、g microcontrollers) now include the functionality.</p><p>　　As is often the case, the availability of UARTs drove the industry to use the RS-232 serial protocol in non-RS-232 ways. Common examples are RS-485

7、 transmissions, opto-isolated transmissions, and transmissions using a single-ended physical layer (i.e. 0 - 3.3V instead of ±5V or ±10V). This note covers the general timing aspects of the serial interface, no

8、t application nuances of handshaking or the physical layer, and so is applicable to all generalized UART applications.</p><p>　　UART Timing</p><p>　　A typical UART frame is shown in Figure 1. It

9、 comprises a Start bit, 8 data bits, and a Stop bit. Other variants are also possible in RS-232 applications - the data packet could be 5, 6, or 7 bits long, there could be 2 Stop bits, and a Parity bit could be inserted

10、 between the data packet and the Stop bit for rudimentary error detection. Figure 1 shows the signaling as seen at a UART's TXD (Transmit Data) or RXD (Receive Data) pins. RS-232 bus drivers invert as well as level s

11、hift, so a logic 1 </p><p>　　Figure 1. A typical UART data frame.</p><p>　　When two UARTs communicate, it is a given that both transmitter and receiver know the signaling speed. The receiver doe

12、sn't know when a packet will be sent, with respect to the receiver clock, hence the protocol is termed asynchronous. The receiver circuitry is correspondingly more complex than that of the transmitter. While the tran

13、smitter simply has to shuffle out a frame of data at a defined bit rate, the receiver has to recognize the start of the frame to synchronize itself, and therefore de</p><p>　　Figure 2 shows a common method u

14、sed by UART receivers to synchronize to a received frame. The receive UART uses a clock which is 16 times the data rate. A new frame is recognized by the falling edge at the beginning of the active-low Start bit, when th

15、e signal changes from the active-high Stop bit or bus idle condition. The receive UART resets its counters on this falling edge, and expects mid Start bit to occur after 8 clock cycles, and the mid point of each subseque

16、nt bit to appear every 16 cl</p><p>　　Figure 2. UART receive frame synchronization and data sampling points.</p><p>　　Timing Accuracy</p><p>　　So the question is: how accurate does

17、the receive UART clock have to be to be sure of receiving data correctly? (Actually, a better question is to ask how far different the transmit and receive UART clocks can be, since the absolute clock rate is unimportant

18、 for the purposes of accurate reception. More on this later.) To answer this, the first point to understand is that because the UART receiver synchronizes itself to the start of each and every frame, we only care about a

19、ccurate data sampling </p><p>　　When do we get a timing error due to transmit-receive clock mismatch? Well, we are attempting to sample each bit at the mid point (Figure 2). If we sample a bit ½ a bit p

20、eriod too early or too late, we will sample at the bit transition and have problems (Figure 3).</p><p>　　Figure 3. UART receive sampling range.</p><p>　　In reality, we can't (reliably) sampl

21、e close to the bit transition point. The dominant reason for this is the finite (and typically slow) transmission rise and fall times, made even slower if overly capacitive cabling is used. A long bus incurs high attenua

22、tion, reducing noise margin, making it more important to sample when the bit level has settled. It is difficult to assess a worst case acceptable sampling range across a bit's period in a quantitive manner. EIA/TIA-2

23、32-F does specify a 4% of b</p><p>　　For Figures 4 and 5 we can determine that the error budget is ±25% and ±37.5% from the optimal bit-centre sampling point for the nasty and normal scenarios resp

24、ectively. This error is equivalent to ±4 or ±6 periods of the x16 UART receive clock. Another error to include in this budget is the synchronization error when the falling edge of the Start bit is detected. The

25、 UART will most likely be designed to start on the next rising edge of its 16x clock after Start bit detection. Since the 16x cloc</p><p>　　We will presume that short-term clock errors (essentially, jitter)

26、are very small, and therefore we are only considering mid-term and long-term errors. These errors boil down to mismatch in the transmit UART and receive UART timing that is consistent during a frame. Since the timing is

27、synchronized at the falling edge of the Start bit, the worst case timing error will be at the last data sampling point, which is the Stop bit. The optimum sampling point for the Stop bit is are its bit-centre, whi</p&

28、gt;<p>　　Now we can calculate our allowable error as a percentage. For the normal scenario, the clock mismatch error can be ±5/152 = ±3.3%, and for the nasty scenario it can be ±3/152 = ±2%. As

29、 hinted earlier, although the problem will materialize at the receive end of the link, clock mismatch is actually a tolerance issue shared between the transmit and receive UARTs. So presuming that both UARTs are attempti

30、ng to communicate at exactly the same bit rate (baud), then the allowable error can be shared, i</p><p>　　Making use of the allowable error budget is helped in systems where both ends of the link are being d

31、esigned at the same time, partly because the tolerance of both ends will be known, and partly because tradeoffs and cost saving can be made. In general a standard, low cost, ceramic resonator with ±0.5% accuracy and

32、 a further ±0.5% drift over temperature and life can be used for the clock source at both ends of the link. This meets the 2% nasty scenario discussed earlier. If the system uses a mas</p><p>　　1. It ma

33、y appear odd that the Stop bit is sampled, but it is. If the Stop bit is detected as a low level instead of the expected high level, UARTs typically report a Frame Error.</p><p><b>　　英文譯文 </b><

34、;/p><p>　　時鐘精度要求確定為UART的通訊</p><p>　　文摘:本應(yīng)用筆記討論時間要求,常用的串行通信協(xié)議執(zhí)行UARTs同步,并展示了如何確定寬容UART源兩端的時鐘的同步連接。</p><p><b>　　背景,</b></p><p>　　這個RS-232規(guī)格可追溯至1962年,當(dāng)它首先被釋放的環(huán)境影響評

35、價(電子工業(yè)協(xié)會)。規(guī)格已經(jīng)改變了,隨著時間的推移,高數(shù)據(jù)率將關(guān)閉相容性之間的差距(電信行業(yè)協(xié)會的癥狀及國際(ITU)標(biāo)準(zhǔn),國際標(biāo)準(zhǔn)化組織(ISO)。當(dāng)前版本的RS-232規(guī)格環(huán)評/ TIA-232-F約會,1997年10月。</p><p>　　這個協(xié)議中獲益的芯片的中型從20世紀(jì)70年代的復(fù)雜性來處理這個標(biāo)準(zhǔn),能以合理的價格。這些電路是一般稱為UARTs(通用異步接收傳輸)。許多大規(guī)模集成電路芯片(包括微控制

36、器)現(xiàn)在包括功能。</p><p>　　通常情況下,UARTs把工業(yè)用RS-232串行協(xié)議在non-RS-232方式。常見的例子是RS-485傳輸,opto-isolated變速箱、變速器結(jié)束單人賽物理層(如下。0 - 3.3V代替±5伏或±10伏特)。這張封面一般時間方面的串行接口,不申請的細(xì)微差別,或?qū)嶓w層,握手,適用于所有的程序。UART廣義</p><p>&l

37、t;b>　　UART時間</b></p><p>　　一個典型的UART架載于本許可證圖1。它包括一個起始位元,8位元的資料,并停止位。也可能在其他變量的數(shù)據(jù)包RS-232應(yīng)用-可5、6、7位長的話,將會有2個停止位、一同等值位可以插入的數(shù)據(jù)間的包,停止位為基本錯誤檢測。圖1顯示如圖一個UART信號傳輸數(shù)據(jù)的TXD(或RXD(接收數(shù)據(jù))。公共汽車司機RS-232反演以及水平移動,所以一個邏輯1負(fù)

38、電壓在公共汽車上,一個邏輯0是一個積極的電壓。</p><p>　　圖1。一個典型的UART數(shù)據(jù)幀。</p><p>　　當(dāng)兩個UARTs溝通,它是一種已知的事實都發(fā)射機和接收機信號速度。知道接收者不知道當(dāng)一個包,就會發(fā)送給接受者的鐘,于是這個協(xié)議是異步的。相應(yīng)的接收機電路是更復(fù)雜的發(fā)射機。而從發(fā)射機只需要簡單地洗牌一幀的數(shù)據(jù)在一個定義編碼傳輸率、接收器已認(rèn)識到開始的幀同步,確定最佳的數(shù)據(jù)

39、采集的最高。</p><p>　　圖2所示的常用方法采用同步UART接收機收到的框架。用一個時鐘的接收UART的數(shù)據(jù)速率16倍。一個新的框架是公認(rèn)的下降沿active-low之初,當(dāng)信號的起始位高電平次數(shù)的變化的停止位或巴士閑置狀態(tài)。接收UART重置其柜臺邊,并且希望這個下降中發(fā)生在8點開始,中期時鐘周期后續(xù)的每一個點對點出現(xiàn)每16時鐘周期。一開始是典型的采樣點的時間來檢查中期的水平仍然很低,確保檢測是起始位下降

40、沿不是噪音。另一個常見的進步是抽樣檢查每一點不只是一次中期位(時鐘計數(shù)8個),但三次(時鐘計數(shù)7、8、9 / 16)。</p><p>　　圖2。收到幀同步和數(shù)據(jù)的UART采樣點。</p><p><b>　　時間精度</b></p><p>　　所以問題是:如何精確的接收UART時鐘都必須確信接收數(shù)據(jù)的正確嗎?實際上,一個更好的問題(就是問迥

41、然不同的傳輸和接收UART鐘可以,因為絕對的時鐘頻率是無足輕重的精確的接待。在這之后。)要回答這個問題,首先是要了解:因為UART接收器本身的同步、每幀,我們只關(guān)心精確的數(shù)據(jù)采集在一架。沒有任何累積誤差超過了框架的停止位、簡化分析,因為我們不得不考慮一幀作為最壞的情況。</p><p>　　當(dāng)我們得到一個計時誤差transmit-receive時鐘匹配嗎?好了,我們都試圖在中期,每點樣點(圖2)。如果我們樣品經(jīng)過

42、一點一點時期太早或太遲了,我們將樣品,過渡和有問題(圖3)。</p><p>　　圖3。接受抽樣范圍。UART</p><p>　　事實上,我們不能(可靠)樣品到發(fā)際線。主導(dǎo)的原因是有限的(通常是慢傳輸?shù)纳仙拖陆?甚至如果過度電容式布線是慢。很長一段時間,減少汽車亦高噪音衰減,使它更重要的邊緣點樣時的水平已經(jīng)得到解決。很難評估一個壞的情況下,可接受的取樣范圍橫跨一點點定量方式的時期。TI

43、A-232-F做環(huán)評/指定一個4%的位周期的一段時間內(nèi)殺死傳播最多,但是這是難以達到的,在192k / bits-1長跑。但讓我們定義兩個數(shù)據(jù)路徑場景的目的都是為了這張紙條。“骯臟的情況考慮,只能從可靠的中期50%的位元時間(圖4)。這等同于一個長、電容RS-232跑?！罢！笨梢栽趫鼍爸?5%的位元時間(圖5),就是到相對溫和的公共汽車(如一米或兩運行緩沖CMOS邏輯層次或RS-485微分副)在設(shè)備上。</p><

44、p>　　圖4?！绑a臟的鏈接的UART獲得50%的取值范圍。</p><p>　　圖5?！罢５倪B接的接受UART 75%的取值范圍。</p><p>　　對數(shù)字第四項、第五項我們能確定這些錯誤的預(yù)算是±10%,且±37.5%從優(yōu)化bit-centre取樣點為急和正常的情景。這個錯誤是相當(dāng)于±4或6期的接收光陰一去不復(fù)返。恢復(fù)UART另一個錯誤,包括預(yù)算同

45、步誤差時的起始位元的下降沿檢測。最有可能的UART來開始下一次設(shè)計的上升沿起始位檢測后分別鐘。自從分別時鐘和收到數(shù)據(jù)流是異步,開始點的下降沿后會發(fā)生分別上升沿,或只是鐘之前,但卻沒有與足夠的啟動時間去使用它。這意味著UART有±1比特同步誤差在建造。那么我們從預(yù)算減少誤差±4或6時鐘周期±3或±5期。</p><p>　　我們會認(rèn)為短期時鐘錯誤(基本上,抖動)非常小,所以我

46、們只考慮中期和長期的錯誤。這些錯誤歸結(jié)為匹配的傳輸和接收UART UART期間定時一致。自從在時間同步的下降沿起始位元,最壞的情況下,時間將會在最后的錯誤數(shù)據(jù)采集,停止位。最佳采樣點停止位,是其bit-centre(16×9.5)= 152 UART接受治療后的時鐘的下降沿起始位元。</p><p>　　現(xiàn)在,我們可以計算出我們的允許誤差作為一個百分比。對于普通的情形下,時鐘匹配誤差±5/15

47、2 =可以,為±3.3%的惡劣情形可以±3/152 =±2%。早些時候,盡管作為暗示問題總會在接收端,鐘不匹配問題實際上是一個寬容之間共享的傳輸和接收UARTs。所以就算這兩UARTs正試圖溝通在相同的比特率(波特),然后在誤差允許可以分享,在任何UARTs兩個人之間的比例。</p><p>　　利用誤差允許的預(yù)算是幫助的兩端連接設(shè)計的同時,部分是因為寬容的兩端,就會知道,部分是因為

48、交易、節(jié)約成本。在一般的標(biāo)準(zhǔn)、低成本、陶瓷諧振器和±0.5%的準(zhǔn)確性和進一步±0.5%的過熱和生活的漂移可用于時鐘源的兩端連接。惡劣的情況之前所討論的2%。如果該系統(tǒng)采用了一個主控制器(通常是一個單片機和PC機),使用一個標(biāo)準(zhǔn)100ppm晶體振蕩器的UART時鐘來源,差不多一半的鏈接錯誤。小心微控制器綜合進行內(nèi)部UARTs波特的頻率。根據(jù)選擇的單片機時鐘,波特率不可能準(zhǔn)確。如果錯誤可以確定,它可以很容易地包含在鏈接錯