外文翻譯---基于eda技術(shù)的hdb3編碼器的設(shè)計(jì)與實(shí)現(xiàn)

1、<p>　　Design based on HDB3 encoder of EDA technology and realizing</p><p><b>　　Summary</b></p><p>　　HDB3 yard is one of the important components in digital baseband communicatio

2、n system, because it does not have direct-flow compositions, it is strong to examine the ability by mistake, have advantages such as performance of clock recovery, etc, recommend the baseband that uses to transmit one of

3、 the yard types as ITU. Have introduced principle and method of HDB3 code at first, has proposed a method based on HDB3 encoder of EDA technology, have simple, with low costs circuit, development period </p><p

4、><b>　　Foreword</b></p><p>　　Third-order high-density bipolar code is an important serial data transmission encoding, digital communication is an important part of the system. And the most comm

5、on NRZ code, compared, HDB3 code has many advantages, such as: eliminating the DC component NRZ code with clock recovery and better anti-jamming performance, making it more suitable for long-distance channel transmission

6、. At the same time, HDB3 error detection code has a strong ability to use HDB3 code when the data transfer sequence,</p><p>　　HDB3 yard High Density Bip01ar Code of three codes, a pair of polarity yard of hi

7、gh density for three steps It is an important code way of serial data transmission, it is one of the important components in the digital communication system too. And most frequently used NRZ yard Non-Return Zero, does n

8、ot return zero yard Compare, HDB3 yard has a lot of advantages, for example: Dispel NRZ direct-flow composition of yard, have clock recovery and better interference-free performance, this makes it su</p><p>

9、　　1 Code rule of HDB3 yard</p><p>　　The code rule of HDB3 yard is as follows:</p><p>　?。?）Vary the news code into AMI yard;</p><p>　　AMI yard Alternate Mark Inversion Full name to s

10、pread number, overturn yard alternatively. This one kind encodes code 0 and 1 of news according to the following rule: Last yard 0 code 0 still, and at code if you can’t turn into, transmit alternative by that yard to 1

11、1, -1, 1, -l;</p><p>　?。?）Check the intersection of AMI and connecting 0 situation with in the yard, as 4 or more of having connect 0 bunches with, keep the form of AMI not changing; Appear 4 or more connect

12、 0 with, 0 turn 4th after the 1 into until the first one the intersection of O and yard With the symbol of polarity, show n is own is V, it is – V – n is own with V;</p><p>　?。?）Check whether not 0 yards of

13、numbers among adjacent v yard is an even number, if is the even number, again present V yard the first one the first 0 yard later turn by B yard B into for 0 times, and is a the first one is the polarities of yard opposi

14、te of O the polarities of B, and make not 0 yards behind begin to replace the change from V yard.</p><p>　　NRZ one yard of course changed into HDB3 yard such as Table 1 shown for example.</p><p>

15、;　　2 Modeling and realizing of HDB3 encoder</p><p>　　Go on data that encode according to encode the principle to convert to AMI yard first while being above-mentioned directly, then go on, add the intersecti

16、on of V and yard, add the intersection of B and yard, operate, will find, transform the intersection of AMI and yards of one ‘the 1’ occasionally into ‘one 1’ Yards of course that polarity form, but after adding B yard a

17、nd operating, only if zero yuans of corresponding polarity might overturn, so there are two pieces of course that signal polar</p><p>　　Analyze the code result of HDB3: V positive to shoulder not alternative

18、 in polarity of yard, remaining 1 and the intersection of B and yard regard as until an organic whole positive to shoulder not alternative too, meet the intersection of V and polarity with the intersection of zero and id

19、entical polarity of in the front of yard at the same time. Therefore has produced the thinking that use FPGA carries on HDB3 one yard of codes: Go on and add V yard first, adds B yard and operates, in this cou</p>

20、<p>　　The digital circuit part of HDB3 encoder is made up of three pieces of module: V yard produced the unit V Gen ,B yard produced the unit B Gen ,A pair of polar conversion units single2double of single polarity

21、 ,Their structure charts.</p><p>　　2. 1 V yard produced the unit V_Gen</p><p>　　V one yard of functions of producing the unit is to connect four in the news code with 0 bunches of detection in f

22、act, namely when connecting with 0 bunches four, vary, succeed V yard fourth 0, but otherwise, keep the former state of the news code exporting. For offer the convenience to encoding the course, transmit yard, say with 2

23、 binary scale one the intersection of code and yuan in the original signal, while going on with V yard, use‘11’ in unison Annotate it, original l yard uses ‘01’ Annot</p><p>　　The original signal NRZ_in prod

24、uced the unit V_Gen through V yard And then signal V_Gen_out wave form:</p><p>　　2. 2 B yard produced the unit B_Gen</p><p>　　B one yard of functions of producing the unit is to guarantee the ad

25、ditional V array after yard is not destroyed ‘Polarity overturns alternatively’ Direct-flow characteristic does not formed, namely when there are a piece of not 0 yards of even number between adjacent V yard, after one i

26、s small for that section if you can’t vary as, destroy by symbol a B of yards each to the first times 0. So, while judging whether some one 0 should be turned into B, should guarantee at first thereafter code yua</p&g

27、t;<p>　　The signal V_Gen_out produced the unit B_Gen through B yard after adding V And then signal B_Gen_out wave form.</p><p>　　2. 3 form polarity – one pair of polar conversion units single 2 double

28、</p><p>　　According to the code rule of HDB3, we can know, the polarity of V yard is positive defeated by the alternative one, remaining 1 and the intersection of B and yard regard as until an organic whole

29、and positive to shoulder not alternative, meet the intersection of V and polarity with the intersection of zero and identical polarity of in the front of yard at the same time. Therefore we can carry on separately polar

30、variety of it to realize. Know from the procedure of the front, ‘V’, ‘B’, ‘1’ Have </p><p>　　Through a pair of polar transformation units of single polarity, 1 including ‘1’, ‘V’, ‘B’ Use 2 binary scale yard

31、 ‘01’ Show – 1 ‘the 1’ ‘the V’ ‘the B’ Use 2 binary scale yard ‘11’ Show, 0 use 2 the intersection of binary scale and yards of ‘the 00’ Show, the advantage encoded like this is, when we regard two high positions of yard

32、 of binary scale that the code transform into as having sign bit that the symbol counts, ‘O1’, ‘11’ , ‘00’ Correspond to 1, – 1, 0 separately. Help us observe the art</p><p>　　Single 3 / pairs of polar hardw

33、are circuit of variety</p><p>　　Download the above-mentioned procedure to the programming device, the code result produced is one pair of level signals of single polarity. This signal is not real HDB3 yard y

34、et, need to be above-mentioned to encode to convert to ‘1’ ‘the 1’ , ‘0’ Level changes the wave form, but work to depend on the digital circuit can’t be finished simply here. The directness way of comparison, utilize the

35、 code result, control many way simulation selector switches to realize, 4 selects a simulation selector s</p><p>　　Utilize many ways to imitate the selector switch CD4052 and realize the circuit connection d

36、iagram that level changed, HDB3_out is that standard HDB3 yard formed finally flows in the picture.</p><p>　　3 conclusions</p><p>　　EDA is a kind of industrial production technology, use the pro

37、grammable chip based on that the hardware describes the language and can describe the hardware to the relevant circuit in the communication system while developing technology in practice, then realize the digital communi

38、cation system with CPLD/ FPGA and combine the design cycle that electronic design automation and artificial technology of the circuit can narrow the products at the same time, reduce the mistake that may happen, improv&l

39、t;/p><p>　　Practice show, use FPGA come, realize the intersection of NRZ and yard to the intersection of HDB3 and conversion of yard than adopt the specialized integrated circuit debug and bring convenience, de

40、fect of overcoming the interference-free difference that the circuit of the discrete hardware brings and difficult to adjust etc., it is short, with low costs and have software development period, it is high to carry out

41、 the speed, the real-time character is strong, upgrade characteristics such as co</p><p>　　基于EDA技術(shù)的HDB3編碼器的設(shè)計(jì)與實(shí)現(xiàn)</p><p><b>　　摘要</b></p><p>　　HDB3碼是數(shù)字基帶通信系統(tǒng)的重要組成部分之一，因?yàn)樗鼪]

42、有直流組成，功能強(qiáng)大，有糾錯(cuò)能力，具有時(shí)鐘恢復(fù)等性能優(yōu)勢，是ITU建議使用的基帶類傳輸碼型之一。本文首先介紹了HDB3碼的原理，提出了基于EDA技術(shù)的HDB3編碼器的實(shí)現(xiàn)方法，其具有電路簡單、成本低、開發(fā)周期短、執(zhí)行速度快、升級(jí)方便等特點(diǎn)。</p><p><b>　　前言</b></p><p>　　HDB3碼(三階高密度雙極性碼)是串行數(shù)據(jù)傳輸?shù)囊环N重要編碼方式，

43、也是數(shù)字通信系統(tǒng)中重要組成部分之一。和最常用的NRZ碼(非歸零碼)相比，HDB3碼具有很多優(yōu)點(diǎn)，例如：消除了NRZ碼的直流成分，具有時(shí)鐘恢復(fù)和更好的抗干擾性能，這使它更適合于長距離信道傳輸。同時(shí)，HDB3碼具有較強(qiáng)的檢錯(cuò)能力，當(dāng)數(shù)據(jù)序列用HDB3碼傳輸時(shí)，若傳輸過程中出現(xiàn)單個(gè)誤碼，其極性交替變化規(guī)律將受到破壞，因而在接收端根據(jù)HDB3碼這一獨(dú)特規(guī)律特性，可檢出錯(cuò)誤并糾正錯(cuò)誤，同時(shí)HDB3碼方便提取位定時(shí)信息。因而HDB3碼作為數(shù)據(jù)傳輸?shù)?/p>

44、一種碼型，應(yīng)用廣泛，成為ITU推薦使用的碼型之一。HDB3碼編譯碼器的實(shí)現(xiàn)有多種途徑，常用的解決方案是應(yīng)用專用的HDB3收發(fā)芯片，如選用專用E1收發(fā)芯片DS2153Q和單片機(jī)實(shí)現(xiàn)該碼制的轉(zhuǎn)換功能。本文提供了一種利用現(xiàn)代EDA技術(shù)，以ACEX系列FPGA芯片EPlK10為硬件平臺(tái)，以Quartus II為軟件平臺(tái)，以VHDL，為開發(fā)工具，適合于FPGA實(shí)現(xiàn)的HDB3編碼器的設(shè)計(jì)方案。</p><p>　　高密度的H

45、DB3碼的編碼守則也稱為3連零守則，一條有極性的高密度信息碼分為三個(gè)步驟編成。這是一種重要的代碼串行數(shù)據(jù)傳輸方式，也是在數(shù)字通信系統(tǒng)中的重要組成部分之一。和最常用的非歸零的NRZ碼和不歸零碼比較，采用HDB3碼具有很多優(yōu)點(diǎn)，例如：消除了NRZ碼的直接流部分組成，有更好的時(shí)鐘恢復(fù)和抗干擾的性能，這使得它更適合在長途傳輸通道中傳輸。同時(shí)，HDB3碼有更強(qiáng)大的誤碼檢測能力，當(dāng)傳輸?shù)臄?shù)據(jù)陣列為HDB3碼時(shí)，如果當(dāng)前的碼單通過在傳輸過程中出錯(cuò)，其

46、極性交替規(guī)律將會(huì)被改變或被破壞，因此在接收端憑借著HDB3碼獨(dú)特的性質(zhì)，就可以檢查錯(cuò)誤和改正錯(cuò)誤，并同時(shí)在相應(yīng)的位置上提取出正確的信息。因此，HDB3碼成為了ITU建議使用的一種數(shù)據(jù)傳輸碼型，被廣泛的應(yīng)用于各個(gè)領(lǐng)域。現(xiàn)在，我們擁有基于不同方式來實(shí)現(xiàn)HDB3碼編譯的設(shè)備，常用的解決方案是采用專門的HDB3收發(fā)芯片，選擇使用專用的E1收發(fā)芯片DS2153Q和單芯片計(jì)算機(jī)作為實(shí)現(xiàn)這種轉(zhuǎn)換功能碼的設(shè)備。這篇研究報(bào)告提供了一種利用現(xiàn)代EDA技術(shù)，

47、它是一種開發(fā)的工具，把ACEX系列FPGA芯片作為硬件平臺(tái)EPlK10，以Quartus II軟件為平臺(tái)，使用</p><p>　　1 HDB3碼的編碼規(guī)則</p><p>　　HDB3碼的編碼規(guī)則如下：</p><p>　?。?）先將一條信息碼元變化成AMI碼；</p><p>　　AMI碼的全稱是傳號(hào)交替反轉(zhuǎn)碼，是通信編碼中的一種，為極性

48、交替翻轉(zhuǎn)碼，分別有一個(gè)高電平和低電平表示兩個(gè)極性。消息代碼中的0在傳輸碼中仍用0，消息代碼中的1在傳輸碼中用+1和-1交替代換。</p><p>　?。?）檢查AMI代碼中的連0情況；</p><p>　　如果出現(xiàn)4個(gè)以下連0的情況，則保持AMI碼的形式不變；如果為4個(gè)或更多的連0時(shí)，從1后開始每4個(gè)0編為1小節(jié)，每小節(jié)的第四個(gè)0變?yōu)榕c前一個(gè)1極性相反的V，+V和-V是交替出現(xiàn)的。<

49、/p><p>　?。?）檢查是否不為0的碼中相鄰V碼的個(gè)數(shù)為偶數(shù)；</p><p>　　如果為偶數(shù)，將第一小節(jié)的第一個(gè)0變成與節(jié)前1極性相反的B，后面的小節(jié)中第一個(gè)0則變?yōu)榕c前小節(jié)中B極性不同的B，而每小節(jié)中V的極性與B相同。</p><p>　　2 HDB3編碼器的建模與實(shí)現(xiàn)</p><p>　　如果直接將要進(jìn)行編碼的數(shù)據(jù)按上述編碼原則先轉(zhuǎn)換成

50、AMI碼，然后進(jìn)行加V碼，加B碼操作，會(huì)發(fā)現(xiàn)轉(zhuǎn)化成AMI碼時(shí)有一個(gè)“+1”、“-1”碼極性形成的過程，而在加B碼操作之后，非零碼元相應(yīng)極性還有可能進(jìn)行反轉(zhuǎn)，因此有兩個(gè)信號(hào)極性產(chǎn)生的過程。</p><p>　　分析HDB3的編碼結(jié)果：V碼的極性是正負(fù)交替的，余下的1碼和B碼看成為一體也是正負(fù)交替的，同時(shí)滿足V碼的極性與前面的非零碼極性一致。由此產(chǎn)生了利用FPGA進(jìn)行HDB3碼編碼的思路：先進(jìn)行加V碼，加B碼操作，在

51、此過程中，暫不考慮其極性，然后將V碼，1碼和B碼分成兩組，分別進(jìn)行極性變換來一次實(shí)現(xiàn)。這樣可以提高系統(tǒng)的效率，同時(shí)減小系統(tǒng)延時(shí)。</p><p>　　HDB3編碼器的數(shù)字電路部分由三個(gè)模塊組成：V碼生成單元(v Gen)，B碼生成單元(B Gen)，單極性一雙極性轉(zhuǎn)換單元(single 2 double)。</p><p>　　2.1 V碼的生成單元</p><p>

52、;　　生成V碼的單位器件實(shí)際上就是實(shí)現(xiàn)檢測消息代碼中0字符串出現(xiàn)的功能，即每當(dāng)連續(xù)的4個(gè)0字符串出現(xiàn)時(shí)可以成功的生成不同的V碼，保持原信息代碼的狀態(tài)。為了使編輯后的信息碼方便傳輸，消息代碼均以2進(jìn)制代碼表示原始信息，當(dāng)出現(xiàn)了V碼時(shí)使用“11”予以注釋，原消息代碼中的1用“01”注釋，0用“00”注釋。</p><p>　　2.2 B碼的生成單元</p><p>　　B碼生成單元的作用是為了

53、確保生成更多的V碼時(shí)陣列中極性交替的規(guī)則不被破壞，不產(chǎn)生直流特性。即在相鄰的V碼間不為偶數(shù)的0小節(jié)的第一個(gè)0不生成B碼。因此，當(dāng)判斷一些0是否需要變?yōu)锽時(shí)應(yīng)當(dāng)確保前一個(gè)3連0是否是含有V碼的小節(jié)，所以必須將當(dāng)前的信息保存至后3個(gè)連0到達(dá)分析入口位置，每一個(gè)小節(jié)都要如此進(jìn)行處理。為了實(shí)現(xiàn)這一目的，首先將每個(gè)V標(biāo)記點(diǎn)分為3個(gè)一組的形式，在下一次同步時(shí)鐘的作用下判斷是否添加B碼。當(dāng)碼元從位移寄存器中輸出時(shí)，可以決定改變成B碼的信息閃爍輸出。&

54、lt;/p><p>　　2.3 極性的生成-單極性-雙極性轉(zhuǎn)換單元</p><p>　　根據(jù)HDB3碼的編碼規(guī)則，我們可以知道對于V碼的極性是不可以主觀判定的，而是用過將剩余的1與B的交集作為一個(gè)有機(jī)的整體排列分辨極性的，V的極性應(yīng)和其所在小節(jié)前的非零代碼相同，因此，我們可以分別的進(jìn)行極性判斷來實(shí)現(xiàn)。從前面的程序知道，“V”、“B”、“1”已經(jīng)分別用雙相碼“11”、“10”、“01”標(biāo)識(shí)之，“

55、0”用“00”標(biāo)識(shí)，所以通過以下的程序我們可以很容易實(shí)現(xiàn)。經(jīng)過單極性一雙極性轉(zhuǎn)化單元，+1(包括“+1”、“+V”、“+B”)用2位二進(jìn)制碼“01”表示，-1(包括“-1”、“-V”、“-B”)用2位二進(jìn)制碼“11”表示，0用2位二進(jìn)制碼“00”表示。這樣進(jìn)行編碼的優(yōu)點(diǎn)是，當(dāng)我們用2個(gè)二進(jìn)制代碼表示時(shí)就得到了正負(fù)的區(qū)分，如“01”“11”“00”便表示為“1”“-1”“0”，可以幫助我們觀察到這樣認(rèn)為確定的結(jié)果。這樣處理后的信號(hào)由B碼生

56、成單元（B Gen）的輸出級(jí)傳遞給單極性-雙極性轉(zhuǎn)換單元（single2double）后由其進(jìn)行極性的判定，更改極性。</p><p>　　將上述的程序下載到可編程器件中，產(chǎn)生的編碼結(jié)果是單極性雙電平信號(hào)。此信號(hào)還不是真正意義上的HDB3碼，需要將上述編碼轉(zhuǎn)換成“+1”、“-1”、“0”的多電平變化波形，而此工作單純依靠數(shù)字電路是無法完成的。比較直接的方式，就是利用編碼結(jié)果，控制多路模擬選擇開關(guān)來實(shí)現(xiàn)，如利用雙4

57、選一的多路模擬選擇開關(guān)CD4052。</p><p><b>　　3 結(jié)論 </b></p><p>　　EDA技術(shù)本身是一種工業(yè)生產(chǎn)技術(shù)，在實(shí)踐中運(yùn)用基于硬件描述語言的可編程芯片開發(fā)技術(shù)可對通信系統(tǒng)中的相關(guān)電路進(jìn)行硬件描述，然后用CPLD／FPGA實(shí)現(xiàn)數(shù)字通信系統(tǒng)，同時(shí)結(jié)合電子設(shè)計(jì)自動(dòng)化和電路仿真技術(shù)即可縮小產(chǎn)品的設(shè)計(jì)周期，降低可能發(fā)生的錯(cuò)誤，提高通信產(chǎn)品的開發(fā)效益

58、。</p><p>　　實(shí)踐表明，運(yùn)用FPGA來實(shí)現(xiàn)NRZ碼到HDB3碼的轉(zhuǎn)換比采用專用集成電路不僅給調(diào)試帶來了方便，克服了分立式硬件電路帶來的抗干擾差和不易調(diào)整等缺陷，而且具有軟件開發(fā)周期短，成本低，執(zhí)行速度高，實(shí)時(shí)性強(qiáng)，升級(jí)方便等特點(diǎn)。而且可以把該電路和它的解碼電路及其他功能電路集成在同一塊FPGA芯片中，減少了外接元件的數(shù)目，提高了集成度，而且有很大的編程靈活性，很強(qiáng)的移植性，因此有很好的應(yīng)用前景。<