外文翻譯--利用ti的msp430系列的嵌入式系統(tǒng)設計(節(jié)選)

1、<p><b>　　中文5030字</b></p><p>　　Embedded Systems Design using the TI MSP430 Series（selection）</p><p>　　This book is intended for the embedded engineer who is new to the field, and

2、 as an introduction and reference for those experienced with micro-controller development, but are new to the MSP430 family of devices. I have assumed that the reader has some experience with microcontroller-based design

3、, either professionally or academically. As an example, the book de- scribes interrupt functionality in detail, but assumes that you, the reader, already know what an interrupt is and how to use it. It is</p><

4、p>　　The MSP430 Family</p><p>　　The MSP430 family is a broad family of low power, feature rich 16-bit microcontrollers from Texas Instruments. They share a common, RISC-type, Neumann CPU core. The '43

5、0 is competitive in price with the 8-bit controller market, and supports both 8 and 16-bit instructions, allowing migration from most similarly sized platforms.</p><p>　　The family of devices ranges from the

6、 very small (1k ROM, 128 bytes for RAM, sub-dollar) up to larger (60k ROM, 2k RAM, with prices in the $10 range) devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices a

7、re split into three families: the MSP430x3xx, which is a basic unit, the MSP430x1xx, which is a more feature-rich family, and the MSP430x4xx, which is</p><p>　　similar to the '1xx, with a built in LCD dr

8、iver. You will find these referred to as '1xx, '3xx, and '4xx devices throughout this book.</p><p>　　Part Numbering Convention</p><p>　　Part numbers for MSP430 devices are determined

9、 based on their capabilities. All device part numbers follow the following template:</p><p>　　MSP430Mt Fa F bMc</p><p>　　M: Memory Type C: ROM</p><p>　　F: Flash P: OTP</p>&l

10、t;p>　　E: EPROM (for developmental use. There are few of these.)</p><p>　　F a, F b:Family and Features 10, 11:Basic</p><p>　　12, 13:Hardware UART</p><p>　　14:Hardware UART, Ha

11、rdware Multiplier 31, 32:LCD Controller</p><p>　　33:LCD Controller, Hardware UART, Hardware Multiplier 41:LCD Controller</p><p>　　43:LCD Controller, Hardware UART</p><p>　　44:L

12、CD Controller, Hardware UART, Hardware Multiplier Mc:Memory Capacity</p><p>　　0:1kb ROM, 128b RAM</p><p>　　1:2kb ROM, 128b RAM</p><p>　　2:4kb ROM, 256b RAM</p><p>　

13、　3:8kb ROM, 256b RAM</p><p>　　4:12kb ROM, 512b RAM</p><p>　　5:16kb ROM, 512b RAM</p><p>　　6:24kb ROM, 1kb RAM</p><p>　　7:32kb ROM, 1kb RAM</p><p>　　8:

14、48kb ROM, 2kb RAM</p><p>　　9:60kb ROM, 2kb RAM</p><p>　　Example: The MSP430F435 is a Flash memory device with an LCD controller, a hardware UART, 16 kb of code memory, and 512 bytes of RAM.<

15、;/p><p>　　The part numbering scheme described above is a bit fragmented. There are common features not consistently represented (type of ADC, number of timers, etc), and there are some other inconsistencies (fo

16、r example, the 33 family has the multiplier, but the 13 and 43s do not). I would recommend against selecting parts based on their numbering scheme. Rather, once you have a vague idea of your requirements, go to the TI we

17、bsite (www.TI.com), and use their parametric sort feature.</p><p>　　Architecture: CPU and Memory</p><p>　　As discussed in chapter 1, the MSP430 utilizes a 16-bit RISC architecture, which is capa

18、ble of processing instructions on either bytes or words. The CPU is identical for all members of the '430 family. It consists of a 3-stage instruction pipeline, instruction decoding, a 16-bit ALU, four dedicate

19、d-use registers, and twelve working (or scratchpad) registers. The CPU is connected to its memory through two 16-bit busses, one for addressing, and the other for data. All memory, including RAM, </p><p>　　T

20、his architecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains available for future growth, rough

21、ly half of the peripheral register space is unused, and only six of the sixteen available special function registers are implemented.</p><p>　　Second, there are plenty of working registers. After years of ha

22、ving one or two working registers, I greatly enjoyed my first experience with the twelve 16-bit CPU scratchpads. The programming style is slightly different, and can be much more</p><p>　　efficient, especial

23、ly in the hands of a programmer who knows how to use this feature to its fullest.</p><p>　　Third, this architecture is deceptively straightforward. It is very flexible, and the</p><p>　　address

24、ing modes are more complicated than most other small processors. But, beyond that, this architecture is simple, efficient and clean. There are two busses, a single linear memory space, a rather vanilla processor core, an

25、d all peripherals are memory-mapped.</p><p>　　CPU Features</p><p><b>　　The ALU</b></p><p>　　The '430 processor includes a pretty typical ALU (arithmetic logic unit).

26、 The ALU handles addition, subtraction, comparison and logical (AND, OR, XOR) operations. ALU operations can affect the overflow, zero, negative, and carry flags. The hardware multiplier, which is not available in all de

27、vices, is implemented as a peripheral device, and is not part of the ALU (see Chapter 6).</p><p>　　Working Registers</p><p>　　The '430 gives the developer twelve 16-bit working registers, R4

28、 through R15. (R0 through R3 are used for other functions, as described later.) They are used for register mode operations (see Addressing Modes, Chapter 8), which are much more efficient than operations which require me

29、mory access. Some guidelines for their use:</p><p>　　Use these registers as much as possible. Any variable which is accessed often should reside in one of these locations, for the sake of efficiency.</p&g

30、t;<p>　　Generally speaking, you may select any of these registers for any purpose, either data or address. However, some development tools will reserve R4 and R5 for debug information. Different compilers will use

31、 these registers in different fashions, as well. Understand your tools.</p><p>　　Be consistent about use of the working registers. Clearly document their use. I</p><p>　　have code, written about

32、 8 months ago, that performs extensive operations on R8,</p><p>　　R9, and R15. Unfortunately, I don't know today what the values in R8, R9 and R15 represent. This was code I wrote to quickly validate an

33、algorithm, rather than production code, so I didn't document it sufficiently. Now, it is relative gibberish. Don't let this happen to you. No matter how obvious or trivial register use seems, document it anyway.&

34、lt;/p><p>　　Constant Generators</p><p>　　R2 and R3 function as constant generators, so that register mode may be used instead of immediate mode for some common constants. (R2 is a dual use register

35、. It serves as the Status Register, as well.) Generated constants include some common single-bit values (0001h, 0002h, 0004h, and 0008h), zero (0000h), and an all 1s field (0FFFFh). Generation is based on the W(S) value

36、in the instruction word, and is described by the table below.</p><p>　　W(S)value in R2value in R3</p><p>　　00————0000h</p><p>　　01(0) (absolute mode)0001h</p><p>

37、　　100004h0002h</p><p>　　110008h0FFFFh</p><p>　　Program Counter</p><p>　　The Program Counter is located in R0. Since individual memory location addresses are 8-bit, but all instr

38、uctions are 16 bit, the PC is constrained to even numbers (i.e. the LSB of the PC is always zero). Generally speaking, it is best to avoid direct manipulation of the PC. One exception to this rule of thumb is the impleme

39、ntation of a switch, where the code jumps to a spot, dependent on a given value. (I.e., if value=0, jump to location0, if value=1, jump to location1, etc.) This process is sho</p><p>　　Example 3.1 Switch Sta

40、tement via Manual PC Control</p><p>　　Outofrange</p><p>　　JmpRangeError</p><p>　　This is a relatively common approach, and most C compilers will implement switch statements with so

41、mething similar. When implementing this manually (i.e., in assembly language), the programmer needs to keep several things in mind:</p><p>　　Always do proper range checking. In the example, we checked for co

42、nditions outside both ends of the valid range. If this is not performed correctly, the code can jump to an unintended location.</p><p>　　Pay close attention to the addressing modes of the jump statements. Th

43、e second doubling of R15, prior to the add statement, is added because the jump statement requires two words when symbolic mode addressing is used.</p><p>　　Be careful that none of your interrupt handlers ha

44、ve the potential to affect your value register (R15 in the example). If the interrupt handler needs to use one of these registers, the handler needs to store the value to RAM first. The most common procedure is to push t

45、he register to the stack at the beginning of the ISR, and to pop the register at the end of the ISR. (See Example 3.2.)</p><p>　　Example 3.2 Push/Pop Combination in ISR</p><p>　　Timer_A_Hi_Inter

46、rupt</p><p>　　DWTimer_A_Hi_Interrupt Status Register</p><p>　　The Status Register is implemented in R2, and is comprised of various system</p><p>　　flags. The flags are all directl

47、y accessible by code, and all but three of them are changed automatically by the processor itself. The 7 most significant bits are undefined. The bits of the SR are:</p><p>　　The Carry Flag (C) Location: SR(

48、0) (the LSB)</p><p>　　Function:Identifies when an operation results in a carry. Can be set or cleared by software, or automatically.</p><p>　　1=Carry occurred</p><p>　　0

49、=No carry occurred</p><p>　　The Zero Flag (Z) Location: SR(1)</p><p>　　Function:Identifies when an operation results in a zero. Can be set or cleared by software, or automatically.&l

50、t;/p><p>　　1=Zero result occurred 0=Nonzero result occurred</p><p>　　The Negative Flag (N)</p><p>　　Location: SR(2)</p><p>　　Function:Identifies when an operation result

51、s in a negative. Can be set or cleared bysoftware, or automatically. This flag reflects the</p><p>　　value of the MSB of the operation result (Bit 7 for byte operations, and bit 15 for word operations).

52、</p><p>　　1=Negative result occurred</p><p>　　0=Positive result occurred</p><p>　　The Global Interrupt Enable (GIE) Location: SR(3)</p><p>　　Function: Enables or disabl

53、es all maskable interrupts. Can be set or cleared by software, or</p><p>　　automatically. Interrupts automa

54、tically reset this bit, and the reti instruction automatically sets it.</p><p>　　1=Interrupts Enabled</p><p>　　0=Interrupts Disabled</p><p>　　The CPU off bit (CPUOff) Location: SR(4

55、)</p><p>　　Function: Enables or disables the CPU core. Can be cleared by software, and is reset by enabled interrupts. None of the memory, peripherals, or clocks are affected by this bit. This bit is used as

56、 a power saving feature.</p><p>　　1=CPU is on 0=CPU is off</p><p>　　The Oscillator off bit (OSCOff) Location: SR(5)</p><p>　　Function: Enables or disables the crystal oscillator cir

57、cuit (LFXT1). Can be cleared by software, and is reset by enabled external interrupts. OSCOff shuts down everything, including peripherals. RAM and register contents are preserved. This bit is used as a power saving feat

58、ure.</p><p>　　1=LFXT1 is on 0=LFXT1 is off</p><p>　　The System Clock Generator (SCG1,SCG0)</p><p>　　Location: SR(7),SR(6)</p><p>　　Function: These bits, along with OSCO

59、ff and CPUOff define the power mode of the device.</p><p>　　The Overflow Flag (V) Location: SR(8)</p><p>　　Function: I dentifies when an operation results in an overflow. Can be set or cleare

60、d by software, or automatically. Overflow occurs when two positive numbers are added together, and the result is negative, or when two negative numbers are added together, and the result is positive.</p><p>

61、　　1=Overflow result occurred 0=No overflow result occurred</p><p>　　Four of these flags (Overflow, Negative, Carry, and Zero) drive program control, via instructions such as cmp (compare) and jz (jump if Zer

62、o flag is set). You will see these flags referred to often in this book, as their function represents a fundamental building block. The instruction set is detailed in Chapter 9, and each base instruction description ther

63、e details the interaction between flags and instructions. As a programmer, you need to understand this interaction.</p><p>　　Stack Pointer</p><p>　　The Stack Pointer is implemented in R1. Like t

64、he Program Counter, the LSB is fixed as a zero value, so the value is always even. The stack is implemented in RAM, and it is common practice to start the SP at the top (highest valid value) of RAM. The push command move

65、s the SP down one word in RAM (SP=SP-2), and puts the value to be pushed at the new SP. Pop does the reverse. Call statements and interrupts push the PC, and ret and reti statements pop the value from the TOS (top of sta

66、ck) back into </p><p>　　Asymmetric push/pop combinations. Every push should have a pop. If you push a bunch of variables, and fail to pop them back out, it will come back to haunt you. If you pop an empty st

67、ack, the SP moves out of RAM, and the program will fail.</p><p>　　Stack encroachment. Remember, the stack is implemented in RAM. If your program has multiple interrupts, subroutine calls, or manual pushes, t

68、he stack will take up more RAM, potentially overwriting values your code needs elsewhere.</p><p>　　Memory Structure</p><p>　　Special Function Registers</p><p>　　Special function reg

69、isters are, as you might have guessed, memory-mapped registers with special dedicated functions. There are, nominally, sixteen of these registers, at memory locations 0000h through 000Fh. However, only the first six are

70、used. Locations 0000h and 0001h contain interrupt enables, and locations 0002h and 0003h contain interrupt flags. These are described in Chapter 3.</p><p>　　Locations 0004h and 0005h contain module enable fl

71、ags. Currently, only two bits are implemented in each byte. These bits are used for the USARTs.</p><p>　　Peripheral Registers</p><p>　　All on-chip peripheral registers are mapped into memory, im

72、mediately after the special function registers. There are two types of peripheral registers: byte-addressable, which are mapped in the space from 010h to 0FFh, and word-addressable, which are mapped from 0100h to 01FFh.&

73、lt;/p><p><b>　　RAM</b></p><p>　　RAM always begins at location 0200h, and is contiguous up to its final address. RAM is used for all scratchpad variables, global variables, and the stack

74、. Some rules of thumb for RAM usage:</p><p>　　The developer needs to be careful that scratchpad allocation and stack usage do not encroach on each other, or on global variables. Accidental sharing of RAM is

75、a very common bug, and can be difficult to chase down. You need to clearly understand how large your stack will become.</p><p>　　Be consistent about use. Locate the stack at the very end of the RAM space, an

76、d place your most commonly used globals at the beginning.</p><p>　　Never allocate more scratchpad than you need, and always deallocate as quickly</p><p>　　as is reasonable. You can never have to

77、o much free RAM. Boot Memory (flash devices only)</p><p>　　Boot memory is implemented in flash devices only, located in memory locations 0C00h through 0FFFh. It is the only hard-coded ROM space in the flash

78、devices. This memory contains the bootstrap loader, which is used for programming of flash blocks, via a USART module.</p><p>　　Information Memory (flash devices only)</p><p>　　Flash devices

79、in the '430 family have the added feature of information memory. This information memory acts as onboard EEPROM, allowing critical variables to be preserved through power down. It is divided into two 128-byte segment

80、s. The first of these segments is located at addresses 01000h through 0107Fh, and the second is at 01080h through 010FFh.</p><p>　　Code Memory</p><p>　　Code memory is always contiguous at the en

81、d of the address space (i.e. always runs to location 0FFFFh). So, for 8k devices, code runs from 0E000h to 0FFFFh, and for the 60k devices, the code runs from 01100h to 0FFFFh. All code, tables, and hard-coded constants

82、reside in this memory space.</p><p>　　Interrupt Vectors</p><p>　　Interrupt vectors are located at the very end of memory space, in locations 0FFE0h through 0FFFEh. Programming and use of these a

83、re described in detail in Chapter 3.</p><p>　　Memory Types</p><p>　　The MSP430 is available with any one of several different memory types. The memory type is identified by the letter immediatel

84、y following "MSP430" in the part numbers. (Example: All MSP430Fxxx parts are flash decices).</p><p><b>　　ROM</b></p><p>　　ROM devices, also known as masked devices, are ide

85、ntified by the letter "C" in the part numbers. They are strict ROM devices, shipped pre-programmed. They have the advantage of being very inexpensive, and may be the best solution for high-volume designs. Howev

86、er, due to high NRE (non-recurring engineering) costs, masked ROM is only cost-efficient when hundreds of thousands (or more) devices are required. They should also only be used for stable designs. If bugs are found too

87、late in the process,</p><p><b>　　OTP</b></p><p>　　OTP is an acronym for "one time programmable", which pretty well describes the functionality of these devices. Identified

88、by the letter "P" in the part number, OTP parts are a good compromise between ROM and flash parts. OTPs are shipped blank, and can be programmed at any time. They are typically more expensive than ROM. They als

89、o require programming, which can be a hindrance in high-volume manufacturing environments. However, OTPs are ideal for low and medium volume applications, and can be a </p><p><b>　　EPROM</b></

90、p><p>　　TI offers windowed EPROM versions of several devices, intended for use in development. They are identified by the letter "E" in the part number. These devices are electrically programmable,

91、and UV-erasable. EPROM devices are only available for a few devices, and typically cost on the order of $50 each. They are not intended for production use, but make ideal platforms for emulating ROM devices in developmen

92、t.</p><p><b>　　Flash</b></p><p>　　Flash devices, identified by the letter "F" in the part number, have become very popular in the past few years. They are more expensive, b

93、ut code space can be erased and reprogrammed, thousands of times if necessary. This capability allows for features such as downloadable firmware, and lets the developer substitute code space for an external EEPROM.</p

94、><p>　　利用TI的MSP430系列的嵌入式系統(tǒng)設計(節(jié)選)</p><p>　　這本書是寫給新進入此領(lǐng)域的嵌入式工程師，作為一個關(guān)于微控制器的開發(fā)經(jīng)驗的介紹和依據(jù)，但新的MSP430系列的設備。我假定讀者對微控制器基礎設計無論是專業(yè)或?qū)W術(shù)上有一定的經(jīng)驗。作為一個例子，這本書詳細描述中斷功能，但假設你，讀者，已經(jīng)知道什么是中斷，以及如何使用它。這也是需重要注意到，雖然在這本書的大部分信息與

95、現(xiàn)成的TI的文件是相同的，這本書的目的是補充，而不是替代的寶貴的信息來源。該用戶指南和應用筆記提供了一個共同的深度和廣度的技術(shù)信息，就很難在重復一個信號源。該這本書的目的是介紹一些最常用的信息，通過一些有用的建議和經(jīng)驗法則。</p><p><b>　　MSP430系列</b></p><p>　　MSP430系列是一種低功率大家族，功能豐富的16位微控制器從得克薩斯

96、儀器。他們都有一個共同的，RISC結(jié)構(gòu)，馮諾依曼的CPU核心。該'430是競爭在價格與8位控制器市場，同時支持8位和16位 指令，通過大多數(shù)同樣大小的平臺進位。</p><p>　　這系列從非常小的（1k ROM, 128 bytes for RAM，美分）到大到（60k ROM, 2k RAM，并在10美元的價格范圍）的設備。目前，至少有40個可用，更經(jīng)常被規(guī)律添加。該設備分為三個系列：MSP430x3

97、xx，這是一個基本單位，MSP430x1xx，這是一個功能更豐富的系列，MSP430x4xx，這是類似于'1 xx，帶有LCD驅(qū)動器內(nèi)置。通過書你會發(fā)現(xiàn)這些相近的'1 xx，'3xx和'4xx裝置。</p><p><b>　　部分編號慣例</b></p><p>　　MSP430器件的數(shù)字部分為基礎來決定他們的能力。所有設備部件編號按

98、照以下模板：</p><p>　　MSP430Mt Fa F bMc</p><p><b>　　M:內(nèi)存類型</b></p><p><b>　　C: ROM</b></p><p><b>　　F: Flash</b></p><p><b&g

99、t;　　P: OTP</b></p><p>　　E: EPROM (為推導使用. 有以下幾種.)</p><p>　　F a, F b: 系列和結(jié)構(gòu)</p><p>　　10, 11: 基本</p><p>　　12, 13: 硬件串口</p><p>　　14: 硬件串口, 硬件乘法器&l

100、t;/p><p>　　31, 32: LCD 控制器</p><p>　　33: LCD 控制器, 硬件串口, 硬件乘法器</p><p>　　41: LCD控制器</p><p>　　43: LCD控制器, 硬件串口</p><p>　　44: LCD 控制器, 硬件串口, 硬件乘法器&

101、lt;/p><p>　　Mc: 電容存儲器</p><p>　　0: 1kb ROM, 128b RAM</p><p>　　1: 2kb ROM, 128b RAM</p><p>　　2: 4kb ROM, 256b RAM</p><p>　　3: 8kb ROM, 256b RAM</p&

102、gt;<p>　　4: 12kb ROM, 512b RAM</p><p>　　5: 16kb ROM, 512b RAM</p><p>　　6: 24kb ROM, 1kb RAM</p><p>　　7: 32kb ROM, 1kb RAM</p><p>　　8: 48kb ROM, 2kb RAM</

103、p><p>　　9: 60kb ROM, 2kb RAM</p><p>　　例如： MSP430F435是帶有LCD控制器的FLASH存儲器設備，硬件串口，16 KB的程序存儲器和512字節(jié)的RAM。</p><p>　　上述這部分編號方案有點零碎。有共同特征的沒有一貫表現(xiàn)（ADC的類型，定時器編號等），并有其他一些不一致的地方（例如，33系列有乘法器，但13和43

104、沒有）。我會建議對選擇部分根據(jù)他們的編號方案。相反，一旦你有一個必要條件您存在模糊的想法，到TI的網(wǎng)站（www.TI.com）使用它們的參數(shù)排序功能。</p><p><b>　　結(jié)構(gòu)：CPU和內(nèi)存</b></p><p>　　正如在第一章中所討論的，MSP430的采用16位RISC結(jié)構(gòu)，這是在任何字節(jié)或字的處理指令的能力。'430家庭的所有成員的CPU是完全