基于手持設(shè)備的多標(biāo)準(zhǔn)解碼器：—h.264avc,avs,和mpeg4的研究

1、上海交通大學(xué)碩士學(xué)位論文基于手持設(shè)備的多標(biāo)準(zhǔn)解碼器：—H.264/AVC, AVS,和MPEG-4的研究姓名：黃照熙申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：計(jì)算機(jī)系統(tǒng)結(jié)構(gòu)指導(dǎo)教師：付宇卓;林福輝20090101II Abstract Cell phone has not only becomes a popular mass communication tool, but also serves as a portable

2、 multimedia player. With the development of 3G/4G technologies, cell phone will benefit from more fast data transmission rate, and TV player on cell phone becomes possible. H.264/AVC is the ne

3、west and most efficient international video coding standard. It is a strong candidate for multimedia transformation over wire/wireless network. AVS becomes Chinese national standard in 2006, and

4、two strong candidates for mobile TV solutions in China: CMMB and CDMB both claim themselves to support A VS. What’s more, considering the prevalent MPEG- 4 portable multimedia devices in the ma

5、rket today, it is necessary to consider MPEG- 4 when talking about multimedia player. Base on the aforementioned factors, this thesis proposes a joint video coding decoder for portable devices.

6、 We select BL@L2 in H.264/A VC, JiZhun@L2.1 in AVS, and ASP@L2 in MPEG- 4 as our research target. We focus our attentions mainly on two categories: one is hardware reuse within same functional

7、 modules among three standards at architecture or algorithmic level. The other is performance enhancement in specified module. In hardware reuse section, we take syntax parser module, entropy de

8、coding module, IDCT (Inverse Discrete Cosin Transformation) module, MC (Motion Compensation) module, and de- blocking module into consideration. In syntax parser module, register array could be reu

9、sed among three standards. For entropy decoding module, table merging method among different variable length table is proposed to reduce code table size. Recursive algorithm is introduced to hand

10、le different IDCT kernel size among three standards. In order to reduce redundant fetching rate in MC process, a reused cache is introduced. What’s more, by properly modifying FIR coefficients

11、 in AVS, H.264/A VC and A VS can reuse one structural FIR set. Considering de- blocking filter in MPEG- 4 is optional, we proposed a structural pipeline design architecture for H.264/A VC and AVS.

12、 On- chip memory could be reused, and boundary strength judgment is mingled. In performance enhancement section, we focus our attentions one three modules: VLD (Variable Length Decoder), MC (Moti

13、on Compensation), and de- blocking module. Feedback path and escape code handling scheme hazard VLD module to achieve high throughput. For MPEG- 4 VLD module, feedback path is not its critical

14、path, but there are four modes for handling escape code. We proposed a parallel detecting method which can handle normal code, escape code, and fixed length code simultaneity. Higher throughput

15、 can be achieved by applying such scheme. For AVS, we break VLD module into two parallel working part: one for code word decoding, the other for symbol decoding. So, long feedback path is

16、broken into two shorter ones. In MC process, a pixel line based, two dimensional cache is proposed for reducing redundant fetching rate. Pipeline working flow with hybrid filtering order is in

17、troduced to de- blocking module for H.264/AVC and AVS. On- chip memory size reduction is benefit from hybrid filtering order, while throughput increase is benefit from three stage pipeline workin