電子工程外文翻譯--一種自校驗(yàn)rs編碼器的分析和設(shè)計(jì)（原文）

1、1A Self Checking Reed Solomon Encoder: Design and AnalysisG.C. Cardarilli, S. Pontarelli, M.Re, A. Salsano {marco.re, g.cardarilli}@ieee.org {pontarelli,salsano}@ing.uniroma2.it University of Rome “Tor Vergata”, Departme

2、nt of Electronic Engineering Rome, ITALYAbstractReed Solomon codes are widely used to identify and correct data errors in transmission and storage systems. Due to the vital importance of these blocks, a very important re

3、search topic is the study of the effects of faults on their behavior. The presented architecture exploits some properties of the arithmetic operations on GF(2n) Galois Field, related to the parity of the binary represent

4、ation of the elements of the field. The encoder has been mapped on an SRAM based FPGA, the self-checking property has been analyzed using a SEU fault model and the performances in terms of area and delay overhead are pre

5、sented.I. INTRODUCTIONHigh reliable data transmission and storage systems frequently use Error Correction Codes (ECC) to protect their data. So they are able to detect errors in binary configuration allowing, under suita

6、ble assumptions, the possibility to correct the coded words. The performance of a code is measured in terms of the maximum number of wrong bits it is able to detect in a coded word and the maximum numbers of bits it is a

7、ble to correct. Other key element is the circuit complexity required for code realization. In fact, the actual implementation of a coding procedure on a real system requires the development of two basic blocks, the encod

8、er and the decoder. The first one, starting from the non coded word computes the code bits realizing the codeword (composed by the data and code bits) that is the protected data to be stored or transmitted. On the contra

9、ry, the decoder receives in input the codeword and checks its correctness eventually correcting the wrong bits. In order to meet the system constraints, frequently these blocks must have high performance in terms of spee

10、d and error correction capabilities in order to process a large amount of data preserving their integrity. Large efforts are devoted to develop codes with increased capabilities of error detection and correction , but, n

11、ormally, larger performances correspond to greater efforts for developing encoders and decoders. Usually system designers focus their attention on the data encoding and decoding performed at the system input and output,

12、supposing that the primary goal is to protect data during their flow inside the system. In this approach very critical points are the input and output circuits, since any error in these circuits may introduce catastrophi

13、c effects on the overall system. A fault in the encoder can produce a non correct codeword, while a fault in the decoder can give a wrong data word even if no errors occurs during the transmission of the codeword. Moreov

14、er these errors will be present in each data flowing in the systems. Therefore great attention must be paid in order to detect and recover faults in encoding and decoding circuitry. These faults are caused either by the

15、conventional sources as, for example, the fail of the technological process, the aging of the electronic devices or by new phenomena related to the new technologies since the shrinking of the elementary devices in the el

16、ectronic systems causes a greater susceptibility of the components to the external environment. One of the main concerns in this field is related to the effects of radiations on silicon devices. A high energy ion during

17、its traveling trough the device can inject charges into the substrate and these charges, due to the electrical biasing, can reach the active elements (transistors) changing the content of storage elements. These effects

18、known as Single Event Upsets (SEU) have been widely studied for applications related to space environment [1], where they are very frequent and predominant with respect to other possible failures . Moreover, SEU’s have b

19、een recently observed and studied at sea level [2] and in aircraft electronics [3] and therefore they are expected to be an important issue in the next years. ECC are widely used in space applications for the design of s

20、pace-borne mass memories [4] and for the transmission of the collected data to the earth stations. These applications require high reliability, and related systems must be tolerant to the effects induced by mechanical st

21、resses, thermal stresses and, especially, radiationProceedings of the 2005 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05) 0-7695-2464-8/05 $20.00 © 2005 IEEE 3modification o

22、f the netlist realized by the original configuration. In fig. 2a we show how a SEU can modify one net segment, interrupting the signal propagation from the CLB. This kind of defect can be modeled as an open defect. Inste

23、ad, in fig. 2b the SEU affecting the configuration memory cause the activation of a routing net that connect the two original nets of the configuration, causing a defect modeled as a short defect.a) open defect caused by

24、 a SEUb) The two net are shortened by the SEUFig. 2. Defect in the routing resourcesIn [5] the open defects are supposed equivalent to stuck-at 0 or stuck-at 1 defect, while the short defect can be characterized as eithe

25、r a wired-AND or a wired-OR model. Two special cases of short defects are stuck-at-0 and stuck-at-1 defects, where a line is shortened with the ground or power line respectively. In [6] the same defect (open and short) a

26、re described, while the effect of these defects at logic level are assumed as unknown logic values for the open defects and indefinite logic values for the short defects. In our work we model the SEU in the registers, th

27、e SEU in the LUTs and the open defects as faults affecting only one resource of the logic netlist implemented in the FPGA. In other words we model these kinds of defects at a higher abstraction level and consider all the

28、se defects as a erroneous value in an input or an output of one of the LUT or memory elements composing the circuit realizing the RS encoder. Analogous considerations can be done for the fault model of short defects: let

29、 us suppose that the short defect affecting two nets named A and B is modeled as a wired-AND (see fig.3). The two nets A and B corresponds to a block with two inputs Ain and Bin and two outputs Aout and Bouts. When the i

30、nputs of this block are the identical, Ain,Bin=(1,1) or (0,0), the output of the block is the same of the fault-free configuration. When the two inputs differs the two outputs provides a value of 0, and therefore only th

31、e output of one net differs from the fault-free configuration. This behavior can be considered as a fault that affect only one component of the logic netlist and therefore we can work at the abstraction level of a logic

32、netlist composed of LUT and flip-flop in order to design the self-checking Reed Solomon encoder.III. BACKGROUND OF REED SOLOMON CODESIt is well know that given a prime number p and a number n ∈ N a field of pn element ca

33、n be constructed. This fields are known as Galois Field GF(pn). For n = 1 the field is composed by the elements [0,1,..p-1] and addition and multiplication are performed modulo p. For n > 1 the Galois field is constru

34、cted as follows:? the elements of the field are the polynomial p(x) of degree n ? 1 with coefficients in GF(p)? addition and multiplication are performed modulo i(x), where i(x) is an irreducible polynomial of degree n.P