機械自動化類畢業(yè)設(shè)計外文翻譯--電子設(shè)計自動化

1、<p><b>　　附錄B 翻譯原文</b></p><p>　　Electronic design automation</p><p>　　Keyword EDA; IC;VHDL language; FPGA</p><p>　　PROCESS DESCRIPTION </p><p>　　Three

2、 obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying language. Then, as the number of lo

3、gic gates per chip passes the million marks, verification of a design's correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing

4、, so that getting a design to meet its timing requirements </p><p>　　As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few i

5、ndividuals with big ideas and a little seed money.</p><p>　　PARLEZ-VOUS SUPERLOG?</p><p>　　A system on a chip comprises both circuitry and the software that runs on it. Such a device may contain

6、 an embedded processor core running a software modem. Most often, after the chip's functionality is spelled out, usually on paper, the hardware com- potent is handed off to the circuit designers and the software is g

7、iven to the pro- grammars, to meet up again at some later date. </p><p>　　The part of the chips functionality that will end up as logic gates and transistors is writ- ten in a hardware design language-Virolo

8、gy or VHDL, while the part that will end up as software is most often described in the programming language C or C++. The use of these disparate languages hampers the ability to describe, model, and debug the circuitry o

9、f the IC and the software in a coherent fashion.</p><p>　　It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specificati

10、on right through to final verification. Just such a new language has been developed by Co-Design Automation Inc., San Jose, Calif. </p><p>　　Before launching such an ambitious enterprise, cofounders Simon Da

11、vidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing language to meet system-on-chip needs. Among the candidates for extension were C, C++, Java, and Verilog. &l

12、t;/p><p>　　A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodo

13、logy. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new co-design language called Superlog. </p><p>　　A natural starting point was a blend of Virology and C sin

14、ce "from an algorithm point of view, a lot of Virology is built on C," explained Davidmann. Then they spiced the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ab

15、ility to describe hardware aspects of the design, such as sequential, combinatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even functions like interfaces, pro

16、tocols, and </p><p>　　It is important for the language to be in the public domain, according to Davidmann. The company has already begun to work with various standards organizations to this end. </p>

17、<p>　　Not to be overlooked is the need for a suite of design tools based on the language. Recently Co-Design identified a number of electronic design automation companies, among them Magma Design Automation, Sente,

18、and Viewlogic, that will develop tools based on Superlog. Co-Design will also develop products for the front end of the design process.</p><p>　　ARACE TO THE FINISH </p><p>　　Not everyone is con

19、vinced that a new language is needed. SystemC, a modeling platform that extends the capabilities and advantages of C/C++ into the hardware domain has been proposed as an alternative. Such large and powerful companies as

20、Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the Open SystemC Initiative to promote their version of the next-generation design platform. To get SystemC off to a running start,

21、the group offers a modeling platform for </p><p>　　The rationale for developing SystemC was straightforward, according to Joachim Kunkel, general manager and vice president of the System Level Design Busines

22、s Unit at Synopsys. It was to have a standard language in which semiconductor vendors, IP vendors, and system houses could exchange system-level IP and executable specifications, and the electronic design automation indu

23、stry could develop interoperable tools. </p><p>　　Supporters of SystemC believe that the would-be standard has to be based on C++ because it allows capabilities to be added to it without leaving the language

24、 standard, Kunkel told JEEE Spectrum. Most software developers use C++ and many systems developers use C++ already to describe their systems at a behavioral level. But till now it has not been possible to describe hardwa

25、re using the language.</p><p>　　The developers of SystemC have solved that problem by defining new C++ class libraries and a simulation kcrne1 that bring to C++ all of the capabilities needed to describe har

26、dware. "These new classes implement new functionality," explained Kunkel. "For example, bit vectors-strings of zeros and ones-and all the operations that you would do on them." The SystemC developers

27、also provided a class of signed and unsigned numbers, the notion of a signal, and other concepts needed to model hardware. </p><p>　　There are still some holes, however. For example, it is still not possible

28、 to synthesize a gate-level netlist from a SystcmC description. Rut synthesis tools for SysteniC would he a natural result of broad acceptance of the language within the user community, according to Kunkel. </p>&

29、lt;p>　　It remains to be seen whether SystemC or Superlog wins out in the end. Least desirable would be an outcome like the impasse between Virology and VHDL, in which both prevailed, forcing electronic design automati

30、on vendors to support both platforms in a wasteful duplication of effort. </p><p>　　THE VERIFICATION NIGHTMARE </p><p>　　If today's complex ICs are tough to design, they are very much toughe

31、r to verify. A variety of tools are available, each with its pros and cons. Emulation translates a design into field-programmable gate arrays (FPGAs). Presumably, if the array works as planned, the final chip will also.

32、The emulation platform also enables designers to try 0111 the software that will run on the ASIC. </p><p>　　The approach, though, is slow. Typical emulation systems run at a few megahertz. "At roughly o

33、ne million cycles per second, designers arc not getting cnough performance out of their emulation systems to verify or understand some of the things that are going on with video generation or high bandwidth communication

34、s," said John Gallagher, director of marketing for Synplicity Inc., Sunnyvale, Calif. They must process a large number of operations to ensure their functionality is correct, he added. </p><p>　　The rea

35、son that emulation systems are so slow, according to Gallagher, is that they route the design through many FPGAs and many boards. Simplicity solution is to use a few high-end FPGAs having over one million gates running a

36、t 100 MHz. Typically, a million FPGA gates translates into 200 000 ASIC gates. Putting nine such chips on a board in a three-by-three array allows designers to represent up to 1.8million ASlC gates. And routing delays ar

37、e greatly curtailed because each chip is no more than</p><p>　　The company% product, called Certify, is not intended to compete with reconfigurable emulation systems, which are very effective at debugging de

38、signs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system, running at speeds that may approach the real thing. </p><p>　　Certify handles three fundamental op

39、erations, said Gallagher. The first is partitioning, or breakings up the ASIC register transfer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the final ASIC

40、gates. Then it does timing analysis. "We haven't just linked together the different tools,” he explained. 'We have taka our synthesis algorithms, between the partitioning capabilities, and laid the timing an

41、alysis across that." </p><p>　　In addition to emulation, two complementary approaches to design verification are simulation and model checking, a type of formal verification. Simulation applies vectors

42、to a software model of a design and checks to sec if the output has the correct value. The approach is straightforward, but is becoming increasingly tortuous as designs become more complicated and the number of possible

43、test vectors mushrooms. So recently, electronic design automation companies have been turning to model checki</p><p>　　The sticking point with model checking is its great difficulty of use. "It is not f

44、or most engineers," said Simon Napper, chief operating officer OF Innol-ogic Systems Inc., San Jose, Calif. "The usage model is very difficult-it checks properties. But the designer isn't familiar with what

45、 P property is-he is used to simulation and static timing." </p><p>　　As a remedy, InnoLogic developed a symbolic simulation tool, which blends simulation and formal verification. It is a Virology simul

46、ator except instead of sending Is and Os through the logic, the too1 propagates symbol or symbols plus binary values.The user gains improved functional coverage dong with much faster verification. </p><p>　　

47、To illustrate, to completely verify a fourbit adder would require 256 binary vectors-and take 256 simulation cycles. With symbols, it takes just one cycle.</p><p>　　Just as with formal verification, there ar

48、e limits to the complexity of the circuits that symbolic simulation can completely verily. Both have trouble with multipliers, for example. "A model checker will grind and grind and never produce a result," exp

49、lained Napper. "But in our tool we take some symbol inputs and switch them to binary values, that reduces the job from a 32- to a 16-bit multiplier. And we report to the user that we were able to verify the upper th

50、e operands." </p><p>　　InnoLogic has announced two Versifies of symbolic simulation. ESI'-XV verifies designs written in Virology. EXP-CV is meant for custom designs and memory blocks. </p>&

51、lt;p>　　THE TIME IS RIGHT </p><p>　　Though the design of ICs with semiconductor geometries below 0.25 pm face challenges throughout development, some of the biggest hurdles occur during physical design, wh

52、en the gates are placed on the chip and the interconnects are routed between them Problems occur here for a number of reasons. First, the capacitance, resistance, and inductance of the interconnects cannot be ignored, as

53、 they were in older, larger technologies. Crosstalk between interconnects; now closer together, must also be co</p><p>　　The solution proposed by Monterey Design Systems Inc., Sunnyvale, Calif., is called gl

54、obal design technology. This proprietary computing approach simultaneously explores, analyzes, and optimizes all aspects of the physical design. The tint product containing the technology is Dolphin, which was announced

55、in April of last year. Dolphin simultaneously places and router each gate and flip-flop using the results or the analysis and maintaining all specified constraints. (Most place- and-route tools </p><p>　　Tim

56、ing closure is top priority for developers of the Blast Fusion physical design system from Magma Design Automations., Cupertino, Calif. Its methodology, called FixedTiming, brings timing within specified limits without i

57、terating between synthesis and physical design .Basically, he approach fixes timing first, then adjusts cell sizes to achieve the timing requirements. Varying the cell sizes always he tool to supply the right drive stren

58、gth or the load.</p><p>　　EDA ON THE WEB </p><p>　　As established electronic design automation companies try to sort out how to utilize the internet in their product Inks, smaller, more agile co

59、mpanies and start-ups arc coining up with innovative products and services, mainly in the areas or design management. A pioneer in this area is Synchronicity Inc., a virtual company headquartered in Marlboro, Mass. Synch

60、ronicity is now being joined by other companies seeking to use the internet to advantage. </p><p>　　The concern of CCAES.COM, Milpitas, Calif a provider of Web-based engineering tools 'for; design automa

61、tion, is the extraction of useful information about ICs, chip sets, and boards from suppliers' Web sites. </p><p>　　The issue, according to Michael Bitzko, president of the company, is that designers of

62、products based on there components need to be able to obtain information about them quickly and route it to their engineering, manufacturing, and procurement departments as quickly as possible. "In a nutshell,” said

63、 Bitzko, "people used to take weeks to get data sheets. Then along cane the Web and PDF-formatted documents. But in order to create, ray, schematic symbols and footprints fur printed circuit boards,</p><p

64、>　　CCAES.COM's products are based on the electronic component interchange (ECIX) standard developed by EDA standards organization SI, Austin, Texas, and on the Extensible Markup Language (XML), that allows the cre

65、ation or Web-bask documents having (more functionality than with the conventional Hypertext Markup Language (HTM1.). The company’s products include QuickData Server, a parametric search engine for electronic component in

66、formation, and Quickdata Miner, which transform information contained </p><p>　　The mission or Genedax Inc., Portland, Ore. is to use the Web to increase designed ability to create and manage large, complex

67、designs, to iron design ICLISC, and to improve access to intellectual property. The company plans to announce a product in the first quarter or the year. John Ott, vice president of sales and marketing, told Sprctmni tha

68、t its products will be based on the operating systems and browsers developed by Microsott Corp., Redmond, Wash. </p><p>　　Also, the company supports a collaborative Web site, www.fatchip.com that shows what

69、the technology can do. The site includes a search engine based on AltaVista technology that searches the Web sites of companies related to design auto illation. Ott elaborated, "We also have a free Internet locator

70、server that lets people use Netmeeting a Microsoft product for remote sharing of computer desktops] and a Web board where you can post questions and get answers." </p><p>　　Other aspects of electronic d

71、esign on the Webs have been slower in taking off than design and information management. But Transim Corp also bared in Portland, Ore, has taken a big step toward Web-based design tools. Its product, Websim, is an interf

72、ace between a Web browser and Simples, the company’s power-supply simulator. Websim allows designers, using Simplis, to simulate designs over the Internet. So rather than poring over data sheets and looking at ranges of

73、values, designers can see actua</p><p>　　Transim is working with suppliers to set up component models so that designers can log on to the supplies Web rite, select parts for their power supply, enter setup o

74、r test conditions, and run the simulation on line. Users need nothing more than a Web browser. The simulation is run on Transim's "ranch" of six strivers from Sun Microsystems. </p><p>　　The co

75、mpany has teamed up with National Semiconductor Corp, Santa Clara, Calif., to provide this service for National's customers. The cost is on a per-use basis and is a minimal US $10. </p><p><b>　　附錄C

76、 翻譯中文</b></p><p><b>　　電子設(shè)計自動化</b></p><p>　　關(guān)鍵字 電子設(shè)計自動化； 集成電路； VHDL語言；現(xiàn)場可編程門陣列</p><p>　　在這個片上系統(tǒng)開始出現(xiàn)的時候，有三個問題一直困擾著集成電路設(shè)計者。首先就是缺乏一些東西即設(shè)計的硬件部件與軟件部件之間缺少統(tǒng)一的語言。這樣由于每一個芯片的

77、邏輯閘門的數(shù)量超過了百萬，因此，對設(shè)計正確性的驗證瞬間比設(shè)計本身更加艱巨。另外，不僅僅是閘門數(shù)量問題，集成芯片的頻率也在加大。因此，為了滿足時間需要，做出一個不用反復設(shè)計的設(shè)計是遙遠的目標。</p><p>　　由于已長期研究電子設(shè)計自動化，對于這方面的關(guān)注經(jīng)常受到一些新建的公司抨擊。那些公司是由幾個志向遠大啟動資金缺乏的人領(lǐng)導。</p><p>　　您說superlog？</p&g

78、t;<p>　　芯片系統(tǒng)由電路和軟件組成運行。這樣的系統(tǒng)一般包含一個嵌入的處理器核運行軟件調(diào)制解調(diào)器。通常，芯片的功能被寫在紙上后，硬件部件就交給了集成電路設(shè)計者，軟件部件就給了程序設(shè)計者，在以后的某個閘門在合起來組在一起。芯片的一部分功能在邏輯閘門核晶體管被寫入硬件描述語言-verilog語言或VHDL語言時結(jié)束。而另外一部分功能將在軟件被描述在編程語言C或C++中結(jié)束。這種不同語言的使用給描述，仿制，調(diào)試集成電路的線路

79、和軟件的條理清晰方面都帶來了很大的不便。</p><p>　　從工業(yè)角度上看我們相信是時候推出一種新的設(shè)計語言處理硬件和軟件的問題，使系統(tǒng)從最初的設(shè)計規(guī)格直達最后的檢驗。加利福尼亞州的協(xié)同設(shè)計自動化公司的san jose發(fā)展了這種新型語言。</p><p>　　在成立這個蒸蒸日上的企業(yè)前，合作者，現(xiàn)經(jīng)營主任simon davidmann和peter flake已經(jīng)得出了為滿足片上系統(tǒng)發(fā)展現(xiàn)

80、有語言的實用性。選為被發(fā)展的現(xiàn)有語言有C,C++,Java和Verilog。</p><p>　　davidmann說一種設(shè)計語言必須滿足三個需求。第一應該連接設(shè)計過程。第二應該使設(shè)計更為高效。第三應該由一種現(xiàn)存的方法演變而來。沒有一種現(xiàn)存的方法滿足這些需求，于是davidmann和flake決定發(fā)明一種新的協(xié)同設(shè)計語言，并命名為superlog。</p><p>　　davidmann解

81、釋說“一個很自然的基準點就是連接verilog語言和C語言，從算法觀點上來看，大多數(shù)verilog語言都是建立在C語言基礎(chǔ)上的?！边@時用比特和VHDL語言與Java語言將其連接起來。從Verilog andVHDL方面，superlog獲得了設(shè)計中描述硬件方面的能力，例如順序邏輯，組合邏輯和多值邏輯。從C和Java方面superlog又集成了動態(tài)處理器和其他軟件編制。甚至像接口程序，活動網(wǎng)絡(luò)路由協(xié)議和狀態(tài)機等現(xiàn)階段仍常被寫在紙上的功能也

82、能被新的語言描述了。為了處理已經(jīng)存在的硬件描述或編程語言的遺留問題，superlog允許verilog語言和C語言模塊輸入并允許其直接使用。</p><p>　　davidmann說這門語言推廣到公共領(lǐng)域使用是非常重要的。公司已經(jīng)開始和不同標準的組織合作工作達到其推廣的目的。</p><p>　　不被忽視是建立在語言上的設(shè)計工具套裝軟件的需要，目前協(xié)同設(shè)計公司已經(jīng)和一些電子設(shè)計自動化公司確

83、立了合作關(guān)系。其中magma 設(shè)計自動化公司，sente公司和viewlogic公司將發(fā)展建立的superlog上的工具。協(xié)同設(shè)計公司將繼續(xù)為設(shè)計程序的前景開發(fā)新的產(chǎn)品。</p><p><b>　　沖向終點的比賽</b></p><p>　　并不是每一個人都相信我們需要新的語言。SystemC語言，一個建模平臺，擴展了C/C++的容量和優(yōu)勢到硬件領(lǐng)域，已經(jīng)被推薦為一

84、個可選擇的方案。許多像synopsys公司，coware公司，lucent技術(shù)公司和德州器具公司等大型權(quán)威的公司已經(jīng)在開放性system C下聯(lián)結(jié)在一起，開始創(chuàng)立他們下一代設(shè)計平臺的版本。為了使system C重新運行，這個組提供了一個建模平臺在他們的網(wǎng)址里免費下載。他們也希望他們的平臺能成為實際的標準。</p><p>　　據(jù)synopsys公司總經(jīng)理兼系統(tǒng)級設(shè)計商業(yè)部副總裁Joachim kunkel說，發(fā)展

85、system c的合理性是顯而易見的。它將是一種標準語言使半導體供應商，IP供應商和系統(tǒng)房屋可交換系統(tǒng)級IP和可執(zhí)行規(guī)格，并且電子設(shè)計自動化工業(yè)能夠發(fā)明一種編寫互用性的工具。</p><p>　　system c的支持者們堅信未來的標準將建立在C++之上因為它允許不放棄語言標準增加新的功能。kunkel告訴IEEE spectrum說大部分軟件開發(fā)者用C++且系統(tǒng)開發(fā)者已經(jīng)運用C++在行為級上描述他們的系統(tǒng)。但是

86、現(xiàn)在仍然不可能用這個語言描述硬件。</p><p>　　通過確定新的C++類庫和模擬型芯，system C的開發(fā)者已解決了上述問題，使得C++擁有了所有的所需的描述硬件的功能。對此，KUNKEL解釋說：“這些新的類實現(xiàn)了新的性能。例如，位向量0和1的字符串，和所有的在其上將實行的操作?！眘ystem C 的開發(fā)者們也提供了一類有符號的數(shù)據(jù)類型和無符號的數(shù)據(jù)類型，另外還有一種信號的概念和仿制硬件所需的其他概念。&l

87、t;/p><p>　　然而，問題依然存在。例如，從一個system C描述上仍舊不能生成一個門級的網(wǎng)表文件。但據(jù)KUNEL說，system C的合成工具將在用戶群體中得出一個語言上被廣泛接受的自然結(jié)果。</p><p>　　system C和Superlog哪一個將取得最終勝利我們?nèi)栽嚹恳源?。最不利的結(jié)果將是像verilog和VHDL之間那樣的僵局，兩者都很盛行，導致電子設(shè)計自動化的商販們支持

88、兩種技術(shù)而浪費雙重的精力。</p><p><b>　　檢驗噩夢</b></p><p>　　如果說當今復雜的集成電路設(shè)計起來很困難，那么檢驗起來就更加困難。每一種可使用的工具都有其缺點和優(yōu)勢。仿真技術(shù)可將一個設(shè)計譯成現(xiàn)場可編程門陣列。據(jù)推測，如果這個陣列按計劃工作，則最終芯片也將工作。這個仿真平臺也能使設(shè)計者們嘗試運用軟件而運行ASIC碼。</p>&

89、lt;p>　　然而走勢很緩慢。典型仿真系統(tǒng)運行幾兆赫。加利福尼亞州Sunnyvale的市場部經(jīng)理John Gallagher說“每秒鐘大約運行一百萬圈，設(shè)計者們不能從他們的仿真系統(tǒng)中有足夠的操作去檢驗或理解一些東西，這些東西將靠新一代視頻技術(shù)或?qū)掝l帶的通信技術(shù)運行。”John補充說“他們必須完成大量的操作以確保功能的正確性”。</p><p>　　據(jù)Gallagher說仿真系統(tǒng)之所以運行緩慢是由于要使設(shè)計按

90、部就班的運行需要通過許多現(xiàn)場可編程門陣列和許多板。synplicity公司的解決方法是用一些高端的現(xiàn)場可編程門陣列。這些現(xiàn)場可編程門陣列以100兆赫運行，擁有超過一百萬門。通常，一百萬現(xiàn)場可編程門陣列門譯成200000ASIC門。將九個這樣的芯片以3×3陣列放置在板上，設(shè)計者可以描述高達1.8百萬的ASIC門。而且運行耽擱將被大大縮短，因為每一個芯片距離陣列中其它任何一個芯片都不超過兩級。</p><p&g

91、t;　　Gallagher解釋說“公司的產(chǎn)品被稱為certify，它并非以與可重構(gòu)的仿真系統(tǒng)競爭為最初目的。并且仿真系統(tǒng)在內(nèi)部設(shè)計過程中對設(shè)計調(diào)試非常有效?！比欢?，它卻真的是系統(tǒng)的藍本，高速運行可能使目標更真實。</p><p>　　Gallagher說certify處理三個基本的操作。第一是分開或打破ASIC寄存器傳送級編碼，使之成為不同的現(xiàn)場可編程門陣列。之后將寄存器傳送級編碼合成為ASIC門，也就是最終合成

92、為ASIC門。此時做時間分析。他解釋說“我們并非只是單純地將兩種不同的工具結(jié)合在一起。我們運用我們合成的算法，使分開的功能相互融合并且將時間分析貫穿于其中。”</p><p>　　除仿真之外，兩種補充的設(shè)計檢驗方法是模擬和一種正規(guī)的檢驗類型--模型檢驗。模擬是在一種設(shè)計和檢驗的軟件模型上應用向量，查看輸出是否有正確的值。方法很直接，但是當設(shè)計越來越多，可能檢驗的數(shù)字向量越來越快速的擴散時，這種方法使用會越來越困難

93、。因此最近電子設(shè)計自動化公司已經(jīng)運用模型檢驗法去驗證設(shè)計是否正確。</p><p>　　模型檢驗的癥結(jié)是使用上的巨大困難。加州圣荷西innologic系統(tǒng)公司操作部經(jīng)理simon napper說“并非大多數(shù)工程師能夠使用它。使用模型非常困難，它為了檢驗性能，但設(shè)計者習慣于模擬和靜態(tài)時序，并不熟悉什么是性能?！?lt;/p><p>　　為了補救，innologic公司開發(fā)了一種象征性的模擬工具。

94、這種模擬工具結(jié)合了模擬和正規(guī)的檢驗。這是一個verilog模擬裝置除了沒有通過邏輯發(fā)送1和0，這種工具傳送符號或帶有二進制數(shù)值的符號。用戶獲得改善的功能保證和更高速的檢驗。為了說明和完全檢驗一個四位微機芯片的加法器，需要256個二元向量，運行256個模擬周期。而使用符號只運行一個周期。</p><p>　　象征性模擬能完全檢驗的電路，僅使用正規(guī)檢驗的話對其復雜性有限制。兩者都在乘數(shù)上有問題。“例如一個模擬檢驗器將

95、不停的旋轉(zhuǎn)運行但從不產(chǎn)生一個結(jié)果?！眓apper解釋說“但是在我們的工具中我們采取一些符號輸入并且將它們轉(zhuǎn)變?yōu)槎M制數(shù)值。這樣從一個32位降至16位的乘數(shù)。并且我們告訴使用者我們可以檢驗超過16的運算對象。”</p><p>　　innologic公司已經(jīng)發(fā)行了兩個版本的象征性模擬。ESP-XV檢驗以verilog寫成的設(shè)計。EXP-CV則意在用戶定制設(shè)計和存儲塊。</p><p><

96、;b>　　時間恰好</b></p><p>　　盡管幾何上在0.25微米以下，運用半導體的集成電路的設(shè)計通過開發(fā)面臨挑戰(zhàn)，但是大的困難一部分發(fā)生在結(jié)構(gòu)設(shè)計上。當門被放置到芯片上時，連接體在它們之間運行。問題發(fā)生在這里，由于一些原因。首先，連接體的電容，電阻和感應系數(shù)不能被忽視。盡管它們屬于更古老更巨大的技術(shù)。由于在一起更為緊密，必須控制連接體之間的串擾。如果最終能夠完成的話，一些通過合成和替代產(chǎn)

97、生的循環(huán)重復可能對于實現(xiàn)所需時序是必要的。</p><p>　　由加州Sunnyvale的monterey設(shè)計系統(tǒng)公司提出的方案稱為全球設(shè)計技術(shù)。這種專利的計算方法對結(jié)構(gòu)設(shè)計的所有方面有開發(fā)分析和改善的效果。第一個包含這項技術(shù)的產(chǎn)品是去年四月生產(chǎn)的Dolphin。Dolphin運用分析結(jié)果維持所有種類的系統(tǒng)規(guī)定參數(shù)以便同時放置和運行每一個門和復振器。（多數(shù)放置和運行工具按順序分析每一種系統(tǒng)規(guī)定參數(shù)的流程圖。）它使

98、每一次放置移動在時間和邏輯上達到最優(yōu)化。</p><p>　　對于位于加州cupertino的正在開發(fā)Blast Fusion結(jié)構(gòu)設(shè)計系統(tǒng)的Magma設(shè)計自動化公司來說，時序收斂是重中之重。它以定時標記為方法，給時序特定的限制，使其不再在合成與結(jié)構(gòu)設(shè)計之間重復?；旧险f，這種方法首先確定時序，然后調(diào)整信元大小以滿足時間的需要。改變信元大小使得工具能為負荷提供適當?shù)尿?qū)動強度。</p><p>