外文文獻原文基于fpga的邏輯分析儀設(shè)計與實現(xiàn)中英文翻譯

1、<p>　　本科畢業(yè)設(shè)計（論文）外文翻譯</p><p>　　題 目 </p><p>　　學(xué)生姓名 </p><p>　　班 級 </p><p>　　學(xué) 號

2、 </p><p>　　院 （系） </p><p>　　專 業(yè) </p><p>　　指導(dǎo)教師 </p><p>　　職 稱

3、 </p><p>　　2017年 月 日</p><p><b>　　原文：</b></p><p>　　Clock Buffer Basics</p><p>　　[author] :Hamilton, Mark1( markh@rennes.ucc.

4、ie);Marnane, William P.1( liam@eleceng.ucc.ie)</p><p>　　[press] :clock buffer with FPGA</p><p>　　Clocks are the basic building blocks for all electronics today. For every data transition in a sy

5、nchronous digital system, there is a clock that controls a register. Most systems use Crystals, Frequency Timing Generators (FTGs), or inexpensive ceramic resonators to generate precision clocks for their synchronous sys

6、tems. Additionally, clock buffers are used to create multiple copies, multiply and divide clock frequencies, and even move clock edges forwards or backward in time. Many clock-bufferi</p><p>　　In today’s typ

7、ical synchronous designs, multiple clock signals are often needed to drive a variety of components. To create the required number of copies, a clock tree is constructed. The tree begins with a clock source such as an osc

8、illator or an external signal and drives one or more buffers. The number of buffers is typically dependent on the number and placement of the target devices. </p><p>　　In years past, generic logic components

9、 were used as clock buffers. These were adequate at the time, but they did little to maintain the signal integrity of the clock. In fact, they actually were a detriment to the circuit. As clock trees increased in speed a

10、nd timing margins reduced, propagation delay and output skew became increasingly important. In the next several sections, we discuss the older devices and why they are inadequate to meet the needs of today’s designs. The

11、 definitions of the c</p><p>　　◆Early Buffers</p><p>　　A clock buffer is a device in which the output waveform follows the input waveform. The input signal propagates through the device and is r

12、e-driven by the output buffers. Hence, such devices have a propagation delay associated with them. In addition, due to differences between the propagation delay through the device on each input-output path, skew will exi

13、st between the outputs. An example of a non-PLL based clock buffer is the 74F244 that is available from several manufacturers. These devices </p><p>　　◆Clock Skew</p><p>　　Skew is the variation

14、in the arrival time of two signals specified to occur at the same time. Skew is composed of the output skew of the driving device and variation in the board delays caused by the layout variation of the board traces. Sinc

15、e the clock signal drives many components of the system, and since all of these components should receive their clock signal at precisely the same time in order to be synchronized, any variation in the arrival of the clo

16、ck signal at its destination will dire</p><p>　　As system speeds increase, clock skew becomes an increasingly large portion of the total cycle time. When cycle times were 50 ns, clock skew was rarely a desig

17、n priority. Even if skew was 20% of the cycle time, it presented no problem. As cycle times dropped to 15ns and less, clock skew requires an ever-increasing amount of design resource. Now typically, these high-speed syst

18、ems can have only 10% of their timing budget dedicated to clock skew, so obviously, it must be reduced.</p><p>　　There are two types of clock skew that affect system performance. The clock driver causes intr

19、insic skew and the printed circuit board (PCB) layout and design is referred to as extrinsic skew. Extrinsic skew and layout procedures for clock trees will be discussed later in this book. The variation of time due to s

20、kew is defined by the following equation:</p><p>　　tSKEW_INTRINSIC = Device Induced Skew</p><p>　　tSKEW_EXTRINSIC = PCB + Layout + Operating Environment Induced Skew</p><p>　　tSKEW

21、= tSKEW_INTRINSIC + tSKEW_EXTRINSIC</p><p>　　Intrinsic clock skew is the amount of skew caused by the clock driver or buffer by itself. Board layout or any other design issues, except for the specification s

22、tated on the clock driver data sheet do not cause intrinsic skew.</p><p>　　◆Output Skew</p><p>　　Output skew (tSK)is also referred to as pin-to-pin skew. Output skew is the difference between de

23、lays of any two outputs on the same device at identical transitions. Joint Electronic Device Engineering Council (JEDEC) defines output skew as the skew between specified outputs of a single device with all driving input

24、s connected together and the outputs switching in the same direction while driving identical specified loads. Figures 2.2 and 2.3 show a clock buffer with common input Cin driving out</p><p>　　◆Part-to-Part

25、Skew</p><p>　　Part-to-part skew (tDSK)is also known as package skew and device-to-device skew. Part-topart skew is similar to output skew except that it applies to two or more identical devices.</p>&

26、lt;p>　　Part-to-part skew is defined as the magnitude of the difference in propagation delays between any specified outputs of two separate devices operating at identical conditions. The devices must have the same inpu

27、t signal, supply voltage, ambient temperature, package, load, environment, etc. Figure 2.4 illustrates tDSK from the preceding example.</p><p>　　Typical part-to-part skew for today’s high performance buffers

28、 is around 500 ps. Propagation Delay</p><p>　　Propagation delay (tPD) is the time between specified reference points on the input and output voltage waveforms with the output changing from one defined level

29、(low) to the other (low). Propagation delay is illustrated in Figure 2.3. Non-PLL based devices in today’s high performance devices range from 3 to 7 ns. PLL-based buffers are able to zero out this propagation delay with

30、 the aid of Phase Detectors, Loop Filters and Voltage Controlled Oscillators (VCOs).</p><p>　　◆Uneven Loading</p><p>　　When using a high-speed clock buffer or PLL, care must be taken to equally

31、load the outputs of the device to ensure that tight skew tolerances are maintained. Inherent in each output of the clock driver is an output impedance that is mostly resistive in nature (along with some inductance and ca

32、pacitance). When each of these resistive outputs is equally loaded, the tight skew specification of the clock driver is preserved. If the loads become unbalanced, the (RC) time constants of the various out</p><

33、;p>　　◆Input Threshold Variation</p><p>　　After the low skew clock signals have been distributed, the clock receivers must accept the clock input with minimal variations. If the input threshold levels of t

34、he receivers are not uniform, the clock receivers will respond to the clock signals at different times creating clock skew. If one load device has a threshold of 1.2 volts and another load device has a threshold of 1.7 v

35、olts and the rising edge rate is 1V/ns, there will be 500 ps of skew caused by the point at which the load device swi</p><p>　　This leaves a 1.2-volt window over voltage and temperature. Components with Comp

36、lementary Metal Oxide Semiconductor (CMOS) rail swing inputs have a typical input threshold of VCC/2 or about 2.5 volts, which is much higher than the TTL level. If the threshold levels are not uniform, clock skew will d

37、evelop between components because of these variations. There are many I/O standards which have emerged and all must be taken into consideration when providing clocks to different subsystems. Table 2.1</p><p>

38、;　　◆Non-PLL Based Clock Drivers</p><p>　　There are two main types of modern clock driver architectures: a buffer-type device (non-PLL) and a feedback-type device (PLL).</p><p>　　In a buffer-styl

39、e (non-PLL) clock driver, the input wave propagates through the device and is “re-driven” by the output buffers. This output signal directly follows the input signal and has a propagation delay (tPD) that ranges from 5 n

40、s to over 15 ns. These devices differ from the buffers in the past such as the 74F244 in that they are designed specifically for clock signals. On a 74F244, there are eight inputs and eight outputs. To create a one to ei

41、ght buffer, all eight inputs are tied togeth</p><p>　　The output skew of this device, if it is not listed on the data sheet, can be calculated by subtracting the minimum propagation delay from the maximum pr

42、opagation delay.</p><p>　　The 10 ns tPD clock driver delay shown in Figure 2.5 does not take into account the affects of the board layout and design. These types of devices are excellent for buffering source

43、 signals such as oscillators where the output phase does not need to match the input. A variety of the non-PLL based buffers are available on the market today and typically range from as few as 4 outputs to as many as 30

44、. Some devices also include configurable I/O and internal registers to divide the output frequencie</p><p>　　Among the highest performance non-PLL based Low Voltage CMOS (LVCMOS) clock buffers available toda

45、y is the B9940L. The B9940L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for

46、 a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V- or 3.3V-compatible and can drive two series te</p><p>　　These devices s

47、till face the problems of device propagation delay. The propagation delay through these devices is about 5 ns. This delay will cause skew in systems where both the reference clock to the buffer and the outputs of the buf

48、fer need to be aligned. These devices also have the drawback that the output waveform is directly based on the input waveform. If the input waveform is a non-50% duty-cycle clock, the output waveform will also have a les

49、s-than-ideal duty cycle. Expensive crystal os</p><p>　　These devices also lack the ability to phase adjust or frequency multiply their outputs. Phase adjustment allows the clock driver to compensate for trac

50、e propagation delay mismatches and setup and hold time differences, and frequency multiplication allows the distribution of high and low frequency clocks from the same common reference. Expensive components and time-cons

51、uming board routing techniques must be used to compensate for the functional shortcomings of these buffer-style clock driver dev</p><p>　　◆PLL-Based Clock Drivers</p><p>　　The second type of clo

52、ck distribution device uses a feedback input that is a function of one of its outputs. The feedback input can be connected internally or externally to the part. If it’s an external feedback, a trace is used to connect an

53、 output pin to the feedback pin. This type of device is usually based upon one or more PLLs that are used to align the phase and frequency of the feedback input and the reference input. Since the feedback input is a refl

54、ecion of an output pin, the propagatio</p><p>　　PLLs have a number of desirable properties that include the ability to multiply clock frequencies, correct clock duty cycles and cancel out clock distribution

55、delays. Many PLL based clock buffers have been brought to market in recent years to aid clock tree designs that require zero propagation delay from the input signal to the output. A completely integrated PLL allows align

56、ment in both the phase and the frequency of the reference with an output. We will look at some of the more prevalent PLL-</p><p>　　◆What is a PLL?</p><p>　　The basic PLL is a feedback system tha

57、t receives an incoming oscillating signal and generates an output waveform that oscillates at the same frequency as the input signal. It is comprised of a phase/frequency detector (PD), a low-pass filter, and a voltage-c

58、ontrolled oscillator as shown in Figure 2.6. In order for the PLL to align the reference (REF) input with an output, the output must be fed back to the input of the PLL. This feedback (FB) input is used as the alignment

59、signal on which all ot</p><p>　　The Phase Frequency Detector (PD) evaluates the rising edge of the REF input with respect to the FB input. If the REF input occurs before the FB input indicating that the VCO

60、is running too slowly, the PD produces a Pump Up signal that lasts until the rising edge of the FB input. If the FB input occurs before the REF input, the PD produces a Pump Down signal that is triggered on the rising ed

61、ge of the FB input and lasts until the rising edge of REF. This Pump Down pulse forces the VCO to run slo</p><p>　　However, the outputs of the CY7B991V operate at the device’s slowest speed while the outputs

62、 of the CY7B994Vwill run at their highest frequency. Therefore, the specifics of the device need to be known if the design will be placed in this condition. (There are now buffers that support dual clock inputs if the lo

63、ss of an input clock is expected.) The filter converts these Pump Up and Pump Down signals into a single control voltage (FCONT) and its magnitude is dependent on the number of previous Pu</p><p>　　◆Zero Del

64、ay Buffer</p><p>　　A zero delay buffer (ZDB) is a device that can fanout one clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited for a v

65、ariety of clock distribution applications requiring tight input-output and out skews. A simplified diagram of a ZDB is shown in Figure 2.7. A ZDB is built with a PLL that uses a reference input and a feedback input. The

66、feedback input is driven by one of the outputs. The phase detector adjusts the output freque</p><p>　　This means that it will have zero delay from the input to the output that drives feedback independent of

67、the loading on that output. Note that this is only the case for the output being monitored by the Feedback input and all other outputs have an input to output delay that is affected by the differences in the output loads

68、. Please see the section “Lead or Lag Adjustment” for a discussion of this topic.</p><p>　　The Cypress Semiconductor CY2308 is a dual bank, general purpose ZDB providing eight copies of a single input clock

69、with zero delay from input to output and low skew between outputs. This popular buffer is designed for use in a variety of clock distribution applications and will be used throughout this book as the typical Zero Delay,

70、PLL-based buffer. The capability to externally connect the feedback path on the device provides skew-control and opens up opportunities for some interesting applica</p><p>　　◆Using External Feedback</p>

71、;<p>　　Many ZDBs have an open external feedback path that is simply closed by driving any output into the FB pin for ZDB operation. However, the feedback path can be used for other interesting applications. Using

72、a discrete delay element in the feedback path will generate outputs that lead the input signal. Sometimes designs require some copies of a clock that are early compared to the remaining copies of the input clock. Figure

73、2.9 shows a circuit implementation to generate such early clocks using a Z</p><p>　　Another simple approach to lead or lag output clocks is to insert trace delay into the feedback path. The outputs of the bu

74、ffer will lead the input by the amount of trace delay added in the feedback path. This approach provides a precise method for delay adjustment. Some designers will embed a very long trace into the board from an output pi

75、n to the feedback pin. At the ends of each trace segment, the designer places pads for zero ohm resistors. This allows for incremental additional delay into </p><p><b>　　譯文：</b></p><p&

76、gt;<b>　　時鐘緩沖器基礎(chǔ)</b></p><p>　　【作 者】:漢密爾頓或哈密爾頓馬克一號（markh @雷恩。UCC。IE）；Marnane，威廉（liam@eleceng.ucc.ie）p.1</p><p>　　【刊 名】時鐘緩沖器與FPGA</p><p>　　單片機；1單片機定義；單片機也被稱為微控制器（Microcontr

77、ol；早期的單片機都是8位或4位的；單片機比專用處理器更適合應(yīng)用于嵌入式系統(tǒng)，因此它；2單片機歷史；單片機誕生于20世紀(jì)70年代末，經(jīng)歷了SCM、M；（1）SCM即單片微型計算機（SingleChi；（2）MCU即微控制器（MicroControl；Philips公司以其在嵌入式應(yīng)用方面的巨大</p><p>　　--------------------------------------------------

78、------------------------------</p><p><b>　　單片機</b></p><p><b>　　1 單片機定義</b></p><p>　　單片機也被稱為微控制器（Microcontroller Unit），常用英文字母的縮寫MCU表示單片機，它最早是被用在工業(yè)控制領(lǐng)域。單片機由芯片內(nèi)

79、僅有CPU的專用處理器發(fā)展而來。最早的設(shè)計理念是通過將大量外圍設(shè)備和CPU集成在一個芯片中，使計算機系統(tǒng)更小，更容易集成進復(fù)雜的而對體積要求嚴(yán)格的控制設(shè)備當(dāng)中。INTEL的Z80是最早按照這種思想設(shè)計出的處理器，從此以后，單片機和專用處理器的發(fā)展便分道揚鑣。</p><p>　　早期的單片機都是8位或4位的。其中最成功的是INTEL的8031，因為簡單可靠而性能不錯獲得了很大的好評。此后在8031上發(fā)展出了MCS

80、51系列單片機系統(tǒng)?；谶@一系統(tǒng)的單片機系統(tǒng)直到現(xiàn)在還在廣泛使用。隨著工業(yè)控制領(lǐng)域要求的提高，開始出現(xiàn)了16位單片機，但因為性價比不理想并未得到很廣泛的應(yīng)用。90年代后隨著消費電子產(chǎn)品大發(fā)展，單片機技術(shù)得到了巨大提高。隨著INTEL i960系列特別是后來的ARM系列的廣泛應(yīng)用，32位單片機迅速取代16位單片機的高端地位，并且進入主流市場。而傳統(tǒng)的8位單片機的性能也得到了飛速提高，處理能力比起80年代提高了數(shù)百倍。目前，高端的32位單片

81、機主頻已經(jīng)超過300MHz，性能直追90年代中期的專用處理器，而普通的型號出廠價格跌落至1美元，最高端的型號也只有10美元。當(dāng)代單片機系統(tǒng)已經(jīng)不再只在裸機環(huán)境下開發(fā)和使用，大量專用的嵌入式操作系統(tǒng)被廣泛應(yīng)用在全系列的單片機上。而在作為掌上電腦和手機核心處理的高端單片機甚至可以直接使用專用的Windows和Linux操作系統(tǒng)。</p><p>　　單片機比專用處理器更適合應(yīng)用于嵌入式系統(tǒng)，因此它得到了最多的應(yīng)用。事

82、實上單片機是世界上數(shù)量最多的計算機?，F(xiàn)代人類生活中所用的幾乎每件電子和機械產(chǎn)品中都會集成有單片機。手機、電話、計算器、家用電器、電子玩具、掌上電腦以及鼠標(biāo)等電腦配件中都配有1-2部單片機。而個人電腦中也會有為數(shù)不少的單片機在工作。汽車上一般配備40多部單片機，復(fù)雜的工業(yè)控制系統(tǒng)上甚至可能有數(shù)百臺單片機在同時工作！單片機的數(shù)量不僅遠超過PC機和其他計算的總和，甚至比人類的數(shù)量還要多。</p><p><b&g

83、t;　　2 單片機歷史</b></p><p>　　單片機誕生于20世紀(jì)70年代末，經(jīng)歷了SCM、MCU、SOC三大階段。</p><p>　　（1）SCM即單片微型計算機（Single Chip Microcomputer）階段，主要是尋求最佳的單片形態(tài)嵌入式系統(tǒng)的最佳體系結(jié)構(gòu)?！皠?chuàng)新模式”獲得成功，奠定了SCM與通用計算機完全不同的發(fā)展道路。在開創(chuàng)嵌入式系統(tǒng)獨立發(fā)展道路上，

84、Intel公司功不可沒。</p><p>　?。?）MCU即微控制器（Micro Controller Unit）階段，主要的技術(shù)發(fā)展方向是：不斷擴展?jié)M足嵌入式應(yīng)用時，對象系統(tǒng)要求的各種外圍電路與接口電路，突顯其對象的智能化控制能力。它所涉及的領(lǐng)域都與對象系統(tǒng)相關(guān)，因此，發(fā)展MCU的重任不可避免地落在電氣、電子技術(shù)廠家。從這一角度來看，Intel逐漸淡出MCU的發(fā)展也有其客觀因素。在發(fā)展MCU方面，最著名的廠家當(dāng)

85、數(shù)Philips公司。</p><p>　　Philips公司以其在嵌入式應(yīng)用方面的巨大優(yōu)勢，將MCS-51從單片微型計算機迅速發(fā)展到微控制器。因此，當(dāng)我們回顧嵌入式系統(tǒng)發(fā)展道路時，不要忘記Intel和Philips的歷史功績。</p><p>　?。?）嵌入式系統(tǒng)階段，單片機是嵌入式系統(tǒng)的獨立發(fā)展之路，向MCU階段發(fā)展的重要因素，就是尋求應(yīng)用系統(tǒng)在芯片上的最大化解決；因此，專用單片機的發(fā)

86、展自然形成了SOC化趨勢。隨著微電子技術(shù)、IC設(shè)計、EDA工具的發(fā)展，基于SOC的單片機應(yīng)用系統(tǒng)設(shè)計會有較大的發(fā)展。因此，對單片機的理解可以從單片微型計算機、單片微控制器延伸到單片應(yīng)用系統(tǒng)。</p><p>　　3 單片機的應(yīng)用領(lǐng)域</p><p>　　目前單片機滲透到我們生活的各個領(lǐng)域，幾乎很難找到哪個領(lǐng)域沒有單片機的蹤跡。導(dǎo)彈的導(dǎo)航裝置，飛機上各種儀表的控制，計算機的網(wǎng)絡(luò)通訊與數(shù)據(jù)傳輸

87、，工業(yè)自動化過程的實時控制和數(shù)據(jù)處理，廣泛使用的各種智能IC卡，民用豪華轎車的安全保障系統(tǒng)，錄像機、攝像機、全自動洗衣機的控制，以及程控玩具、電子寵物等等，這些都離不開單片機。更不用說自動控制領(lǐng)域的機器人、智能儀表、醫(yī)療器械了。因此，單片機的學(xué)習(xí)、開發(fā)與應(yīng)用將造就一批計算機應(yīng)用與智能化控制的科學(xué)家、工程師。</p><p>　　單片機廣泛應(yīng)用于儀器儀表、家用電器、醫(yī)用設(shè)備、航空航天、專用設(shè)備的智能化管理及過程控制

88、等領(lǐng)域，大致可分如下幾個范疇：</p><p>　?。?）在智能儀器儀表上的應(yīng)用</p><p>　　單片機具有體積小、功耗低、控制功能強、擴展靈活、微型化和使用方便等優(yōu)點，廣泛應(yīng)用于儀器儀表中，結(jié)合不同類型的傳感器，可實現(xiàn)諸如電壓、功率、頻率、濕度、溫度、流量、速度、厚度、角度、長度、硬度、元素、壓力等物理量的測量。采用單片機控制使得儀器儀表數(shù)字化、智能化、微型化，且功能比起采用電子或數(shù)

89、字電路更加強大。例如精密的測量設(shè)備（功率計，示波器，各種分析儀）。</p><p>　?。?）在工業(yè)控制中的應(yīng)用</p><p>　　用單片機可以構(gòu)成形式多樣的控制系統(tǒng)、數(shù)據(jù)采集系統(tǒng)。例如工廠流水線的智能化管、電梯智能化控制、各種報警系統(tǒng)，與計算機聯(lián)網(wǎng)構(gòu)成二級控制系統(tǒng)等。</p><p>　?。?）在家用電器中的應(yīng)用</p><p>　　可以

90、這樣說，現(xiàn)在的家用電器基本上都采用了單片機控制，從電飯褒、洗衣機、電冰箱、空調(diào)機、彩電、其他音響視頻器材、再到電子秤量設(shè)備，五花八門，無所不在。</p><p>　?。?）在計算機網(wǎng)絡(luò)和通信領(lǐng)域中的應(yīng)用</p><p>　　現(xiàn)代的單片機普遍具備通信接口，可以很方便地與計算機進行數(shù)據(jù)通信，為在計算機網(wǎng)絡(luò)和通信設(shè)備間的應(yīng)用提供了極好的物質(zhì)條件，現(xiàn)在的通信設(shè)備基本上都實現(xiàn)了單片機智能控制，從手機

91、，電話機、小型程控交換機、樓宇自動通信呼叫系統(tǒng)、列車無線通信、再到日常工作中隨處可見的移動電話，集群移動通信，無線電對講機等。</p><p>　?。?）單片機在醫(yī)用設(shè)備領(lǐng)域中的應(yīng)用</p><p>　　單片機在醫(yī)用設(shè)備中的用途亦相當(dāng)廣泛，例如醫(yī)用呼吸機，各種分析儀，監(jiān)護儀，超聲診斷設(shè)備及病床呼叫系統(tǒng)等等。</p><p>　　（6）在各種大型電器中的模塊化應(yīng)用&l

92、t;/p><p>　　某些專用單片機設(shè)計用于實現(xiàn)特定功能，從而在各種電路中進行模塊化應(yīng)用，而不要求使用人員了解其內(nèi)部結(jié)構(gòu)。如音樂集成單片機，看似簡單的功能，微縮在純電子芯片中（有別于磁帶機的原理），就需要復(fù)雜的類似于計算機的原理。如：音樂信號以數(shù)字的形式存于存儲器中（類似于ROM），由微控制器讀出，轉(zhuǎn)化為模擬音樂電信號（類似于聲卡）。</p><p>　　在大型電路中，這種模塊化應(yīng)用極大地縮小

93、了體積，簡化了電路，降低了損壞、錯誤率，也方便于更換。</p><p>　?。?）單片機在汽車設(shè)備領(lǐng)域中的應(yīng)用</p><p>　　單片機在汽車電子中的應(yīng)用非常廣泛，例如汽車中的發(fā)動機控制器，基于CAN總線的汽車發(fā)動機智能電子控制器，GPS導(dǎo)航系統(tǒng)，abs防抱死系統(tǒng)，制動系統(tǒng)等等。</p><p>　　此外，單片機在工商，金融，科研、教育，國防航空航天等領(lǐng)域都有著十

94、分廣泛的用途。</p><p><b>　　4 單片機介紹</b></p><p>　　單片機又稱單片微控制器,它不是完成某一個邏輯功能的芯片,而是把一個計算機系統(tǒng)集成到一個芯片上。相當(dāng)于一個微型的計算機，和計算機相比，單片機只缺少了I/O設(shè)備。概括的講：一塊芯片就成了一臺計算機。它的體積小、質(zhì)量輕、價格便宜、為學(xué)習(xí)、應(yīng)用和開發(fā)提供了便利條件。同時，學(xué)習(xí)使用單片機是了

95、解計算機原理與結(jié)構(gòu)的最佳選擇。</p><p>　　單片機內(nèi)部也用和電腦功能類似的模塊，比如CPU，內(nèi)存，并行總線，還有和硬盤作用相同的存儲器件，不同的是它的這些部件性能都相對我們的家用電腦弱很多，不過價錢也是低的，一般不超過10元即可用它來做一些控制電器一類不是很復(fù)雜的工作足矣了。我們現(xiàn)在用的全自動滾筒洗衣機、排煙罩、VCD等等的家電里面都可以看到它的身影！它主要是作為控制部分的核心部件。</p>

96、<p>　　它是一種在線式實時控制計算機，在線式就是現(xiàn)場控制，需要的是有較強的抗干擾能力，較低的成本，這也是和離線式計算機的（比如家用PC）的主要區(qū)別。</p><p>　　單片機是靠程序運行的，并且可以修改。通過不同的程序?qū)崿F(xiàn)不同的功能，尤其是特殊的獨特的一些功能，這是別的器件需要費很大力氣才能做到的，有些則是花大力氣也很難做到的。一個不是很復(fù)雜的功能要是用美國50年代開發(fā)的74系列，或者60年代的

97、CD4000系列這些純硬件來搞定的話，電路一定是一塊大PCB板！但是如果要是用美國70年代成功投放市場的系列單片機，結(jié)果就會有天壤之別！只因為單片機的通過你編寫的程序可以實現(xiàn)高智能，高效率，以及高可靠性！</p><p>　　單片機內(nèi)部也用和電腦功能類似的模塊，比如CPU，內(nèi)存，并行總線，還有和硬盤作用相同的存儲器件，不同的是它的這些部件性能都相對我們的家用電腦弱很多，不過價錢也是低的，一般不超過10元即可...

98、...用它來做一些控制電器一類不是很復(fù)雜的工作足矣了。我們現(xiàn)在用的全自動滾筒洗衣機、排煙罩、VCD等等的家電里面都可以看到它的身影！它主要是作為控制部分的核心部件。</p><p>　　它是一種在線式實時控制計算機，在線式就是現(xiàn)場控制，需要的是有較強的抗干擾能力，較低的成本，這也是和離線式計算機的（比如家用PC）的主要區(qū)別。</p><p>　　由于單片機對成本是敏感的，所以目前占統(tǒng)治地位

99、的軟件還是最低級匯編語言，它是除了二進制機器碼以上最低級的語言了，既然這么低級為什么還要用呢？很多高級的語言已經(jīng)達到了可視化編程的水平為什么不用呢？原因很簡單，就是單片機沒有家用計算機那樣的CPU，也沒有像硬盤那樣的海量存儲設(shè)備。一個可視化高級語言編寫的小程序里面即使只有一個按鈕，也會達到幾十K的尺寸！對于家用PC的硬盤來講沒什么，可是對于單片機來講是不能接受的。 單片機在硬件資源方面的利用率必須很高才行，所以匯編雖然原始卻還是在大量使