外文翻譯-----單片機(jī)數(shù)據(jù)采集接口

1、<p>　　附錄二 外文原文及翻譯</p><p>　　Single-Chip Data Acquisition Interface</p><p>　　Gintaras Paukstaitis</p><p><b>　　Abstract </b></p><p>　　This paper presents

2、a single-chip data acquisition interface. It’s devoted for from one to eight analogous signals input to RAM of IBM PC or compatible computers. Maximal signal sampling rate is 80 kHz. Interface has programmable gain for a

3、nalogous signals as well as programmable sampling rate and number of channels. Some functional unit was designed  using synthesis from VHDL with help of Synopsys. Interface was based on 1 mm CMOS process from ATMEL-

4、ES2. It was verified using kit for DFWII of C</p><p>　　Table of contains Abstract 1.  Introduction 2.  Steps of Designing 3.  Analogous Part 4.  Digital Part 5. Interface Testing

5、6. Creation of Layout 7. Technical Data 8.  Conclusions 9.  Acknowledgements 10. References 1.  Introduction </p><p>　　Nowadays units with VLSI are widely used in the world. It is really

6、important for miniaturisation. Circuits with some IC redesigned to VLSI reduce its area many times. By the way, relatively VLSI itself becomes cheaper. While using units with VLSI gets less damage, as well as uses less p

7、ower. Using of CAD makes easier and faster complicated IC designing. Cheaper computers give an opportunity to get servers not only for big companies and institutions of education but also for medium firms. This s</p&g

8、t;<p>　　2.  Steps of Designing </p><p>　　A circuit was designed according to a basic circuit. That is way Semi-Custom Design method was used. The flow-chart of interface is shown in the Fig. 2.

9、 It was necessary to use 8 operational amplifiers (OA) to fit eight analogous signals to A/D converter's limits. OA has programmable established gain. In many cases it could let analogous signal without any addition

10、al amplifiers to give to A/D converters. Gain for every OA separately fixed with Gain Control Block. Two converters change analogo</p><p>　　3. Analogous Part </p><p>　　Alternating analogous volt

11、age signals are changed to pulsate one from 0 to +5 V signal in the analogous part of interface. As converter is made of CMOS elements and it’s power supply is 0 and +5 V so it can change only signal between 0 and +5 V l

12、imits. In order to reduce converting mistake converters are given analogous signal which should as close as possible to the limits. Programmable OA makes stronger analogous signals. It has 16 possible gains which are sel

13、ected with the help of four bit co</p><p>　　4. Digital Part </p><p>　　Control Block of interface was designed while changing discrete components of board to accordingly chip components of ES2 li

14、brary. Some changes through different control of ES2 library and prototype board analogous elements were made. It was timer described in VHDL for its designing. Three models were created: two models for clock frequency d

15、ividing from coefficient which length is 16 and 8 bit and another one for one-shot mode. The length of control word is 8 bit. Standard packages of IEEE libr</p><p>　　Table 1. Summary of the Counter’s Area Op

16、timisation </p><p>　　5. Interface Testing </p><p>　　It was simulated full work for the verification of interface with Verilog-XL. Test programs are wrote in STL: control words fed for OA, Chann

17、el Control Block and timer, data scanning. Single-chip interface is good-working and has technical data as shown in Table 2. 6. Creation of Layout </p><p>　　Analogous elements used in layout

18、were changed from Verilog HDL to physical. They are put on periphery of the chip. It is done because they have pads which are connected with IC package's pins. The pads of digital signals are put separately from anal

19、ogous elements. The reason is that analogous elements have two power supply rails. And digital pads have four rails. Corner elements witch supply powers for periphery pads have four rails too. Therefore analogous element

20、s are separated from corner el</p><p>　　7. Technical Data</p><p>　　8.  Conclusions </p><p>　　In this paper I have presented a single chip analogous data acquisition interface.

21、Complex functional blocks was described in VHDL. With help of Synopsys full functional unit was synthesised. Units were excess, so the optimisation was done for small area. After transporting to Cadence synthesised units

22、 were worked according to the set function. All circuits of interface, including models of analogous elements, were verified with Verilog-XL. The chip layout based on 1.0 mm CMOS process from ATMEL</p><p>　　

23、9. Acknowledgements </p><p>　　Thanks to prof. R.Ðeinauskas for his directing, dipl. eng. A.Maèiulis to give me a basic circuit of prototypic board and assoc. prof. R.Benisevièiûtë fo

24、r they valuable suggestions. </p><p>　　10. References </p><p>　　[1] Data Acquisition Boards Catalogue. Kethler MetraByte, 1996-1997, vol. 28. [2] Zanalabedin Navabi. Beginning VHDL: An Introduc

25、tion Language Concept, Boston-Massachusetts, 1994. [3] User Guide for the ES2 0.7mm/1.0mm CMOS Library Design Kit on CADENCE DFWII Software (Design Kit/User Guide Version: 4.1e1), July, 1996.</p><p><b&g

26、t;　　單片機(jī)數(shù)據(jù)采集接口</b></p><p>　　摘要   本文提出了一種單芯片的數(shù)據(jù)采集接口。這是專門為從1到8通道的模擬信號(hào)輸入到RAM的IBM PC或兼容計(jì)算機(jī)。最大信號(hào)的采樣率為80千赫。接口可編程增益為模擬的信號(hào)，以及可編程的采樣率和聲道數(shù)。一些職能單位的目的是利用合成的VHDL與幫助下， Synopsys的。接口是基于1毫米CMOS工藝向Atmel -沙二段。這是核實(shí)使

27、用試劑盒的DFWII Cadence的。在布局布線工具，包括Cadence被用來獲取電路布局。 表中包含 摘要 1 導(dǎo)言 2 設(shè)計(jì)步驟 3 類似的部分 4 數(shù)字部分 5 接口測(cè)試 6 建立布局 7 技術(shù)數(shù)據(jù) 8 結(jié)論 9 鳴謝 10 參考資料 1 導(dǎo)言 現(xiàn)在單位，超大規(guī)模集成電路，廣泛應(yīng)用于世界各地。這是非常重要的小型化。一些IC電路重新設(shè)計(jì)，以減少其職權(quán)范圍內(nèi)的VLSI許多倍。順便說一下，超大規(guī)模集

28、成電路本身相對(duì)變得便宜。雖然與使用單位的VLSI得到較少的損害，以及使用較少的電力。利用CAD技術(shù)使得更容易和更快的復(fù)雜的IC設(shè)計(jì)。廉價(jià)電腦提供一個(gè)機(jī)會(huì)讓服務(wù)器不僅對(duì)大公司和教育機(jī)構(gòu)，而且還為中型公司。這步鼓勵(lì)這種復(fù)雜的電</p><p>　　6 。建立布局    類似的內(nèi)容用于布局是由Verilog HDL語言身體。他們把周圍的芯片。這是因?yàn)樗麄冇袎|是與IC封裝的引腳。港口及機(jī)場(chǎng)發(fā)展策略

29、的數(shù)字信號(hào)分別提出類似的內(nèi)容。原因是，類似的內(nèi)容有兩個(gè)電源軌。和數(shù)字墊有4個(gè)導(dǎo)軌。角元素女巫供應(yīng)權(quán)力邊緣墊也有4個(gè)導(dǎo)軌。因此，類似的內(nèi)容是分開角落要素的特殊組成部分。類似的電源是由這些特殊因素的ADC和辦公自動(dòng)化。設(shè)計(jì)師引導(dǎo)自動(dòng)方法用于建立布局。這是使用自動(dòng)標(biāo)準(zhǔn)邏輯布局和布線工具Cadence的。為了降低噪聲的影響，地區(qū)標(biāo)準(zhǔn)邏輯已建立盡可能從類似內(nèi)容的一部分。類似的內(nèi)容是它們之間的連接外集成電路。如果芯片辦公參數(shù)是不夠的，可以放在境外使

30、用的辦公自動(dòng)化。芯片的布局顯示圖5 。芯片有很多空白區(qū)域，因?yàn)樗拿娣e是有限的墊的邊緣?？偯娣e所需要的是21,5平方毫米（ 4,7 '4 ， 6毫米） ，以積極的方面一點(diǎn)六平方毫米（ 1,39 '1 ， 17毫米） 。 7 。技術(shù)數(shù)據(jù) 一些投入8 交流輸入電壓范圍（ 0,1-2,0 ） V 信號(hào)的第8位 最大采樣率80千赫茲 最小采樣率13赫茲 5V的電源供應(yīng)器+ 8 。</p&g