外文翻譯--高速數(shù)據(jù)采集系統(tǒng)的設計

1、<p>　　中文4300字，2730單詞</p><p>　　畢業(yè)設計(論文)外文資料翻譯</p><p>　　附件：1.外文資料翻譯譯文；2.外文原文</p><p>　　高速數(shù)據(jù)采集系統(tǒng)的設計</p><p>　　張俊杰，章鳳一，葉家駿</p><p>　?。ㄉ虾４髮W特種光纖和光纖接入教育部重點實驗室部，

2、上海200072）</p><p>　　摘要：為滿足雷達信號采集的要求，設計了一種基于PCI總線的12 bit100 MS / s的數(shù)據(jù)采集系統(tǒng)。該系統(tǒng)可實現(xiàn)6 GB數(shù)據(jù)的實時采集和存儲。可編程邏輯器件控制數(shù)據(jù)收集，存儲和傳輸。使用PCI主模式的PCI數(shù)據(jù)傳輸，傳輸速率達到60M字節(jié)/秒，（30兆赫的模擬信號）收集到的信號的信噪比可以達到55 dB。</p><p>　　關鍵詞：PCI控制

3、器;可編程器件;抖動。</p><p><b>　　1.總述</b></p><p>　　隨著通信，雷達等領域的快速發(fā)展，所需處理模擬信號的帶寬和動態(tài)范圍也越來越大，DAC采樣速度和精度要求越來越高。高速度和高精度的數(shù)據(jù)收集所需的存儲器帶寬變得越來越大，因此，如何提高數(shù)據(jù)存儲器帶寬已經成為高速數(shù)據(jù)采集系統(tǒng)設計的瓶頸之一。</p><p>　　雷

4、達系統(tǒng)的數(shù)據(jù)采集系統(tǒng)時鐘采樣頻率要求是至少100兆赫，對至少10位DAC分頻。而現(xiàn)有的計算機系統(tǒng)滿足不了雷達系統(tǒng)的實時傳輸?shù)囊?。但雷達信號的有用信息只占其中一小部分。如圖1，因此，只要將有用信息采集和儲存，則可實現(xiàn)雷達信號樣本實時存儲。</p><p><b>　　圖1</b></p><p>　　根據(jù)雷達信號采集和存儲的特性，本文設計一個12 bit100 MS

5、/ s的數(shù)據(jù)采集系統(tǒng)。該系統(tǒng)采用了PCI總線連接到計算機，數(shù)據(jù)采集系統(tǒng)利用板卡大容量信息對有用信息進行實時處理，數(shù)據(jù)采集由系統(tǒng)外部出發(fā)信號控制。</p><p><b>　　2.數(shù)據(jù)采集卡框架</b></p><p>　　整個采集系統(tǒng)分為以下四個部分：模擬信號調制部分，時鐘脈沖處理模塊，數(shù)據(jù)緩存模塊，數(shù)據(jù)傳輸和觸發(fā)模塊。如圖2所示。</p><p&

6、gt;<b>　　圖2</b></p><p><b>　　2.1模擬信號調制</b></p><p>　　模擬信號的調制包括：模擬信號前放，信號數(shù)控增益，單端轉差分布。模模擬信號前置運放采用AD9631實現(xiàn)輸入信號的阻抗匹配及信號的低通濾波。在一個雷達系統(tǒng)中，從不同的雷達站收集掃描目標的雷達信號振幅是不同的，并且為了提高采集系統(tǒng)的信噪比，應使A

7、DC的模擬輸入信號的幅度接近滿幅。所以將一個壓控增益運算放大器AD603芯片加到前置運算放大器之后，以調節(jié)ADC輸入信號的范圍。電壓控制AD603的增益芯片的模擬帶寬在90 MHz時， 增益范圍-11 dB一30 dB。由一片8位DAC芯片產生壓控芯片的的增益電壓，DAC的芯片選擇MAX503 MAXIM公司出品，芯片數(shù)字輸入由FPGA控制和產生。數(shù)據(jù)采集系統(tǒng)的ADC 是由AD公司12位100兆赫AD9432 的芯片，該模擬信號為45M

8、Hz仍然具有65 dB的信噪比。由于該ADC模擬信號為差分輸入差，因此,從壓控增益芯片AD603輸出的模擬信號經過單端轉差分芯片AD8138連接到ADC芯片上，從ADC輸出的12 bit數(shù)字信號直接連接到FPGA芯片上。</p><p><b>　　2.2 時鐘模塊</b></p><p>　　為了增加所述采集系統(tǒng)的靈活性和通用性，該ADC采樣時鐘芯片可以是從外部時鐘

9、，也可以從內部時鐘。采樣時鐘的選擇由板卡跳線器決定。外部時鐘通過SMA連接器連接到電路板上，外部時鐘信號為TTL電平，由于ADC的采樣時鐘需要PECL電平，因此，外部時鐘時鐘由PECL電平轉換芯片MClOELl6連接到時鐘選擇模塊。 ADC的內部時鐘是由該系統(tǒng)的數(shù)控時鐘模塊生產。 時鐘模塊選擇頻率合成器是NC SY89429。時鐘輸出的范圍在25兆赫至400兆赫之間，用于PECL輸出信號，可直接連接到ADC的采樣時鐘。該頻率合成器的時鐘

10、輸出可被芯片的11位數(shù)字信號控制，可以精確調節(jié)輸出時鐘精度至1兆赫茲。 11數(shù)字信號由FPGA控制。在數(shù)據(jù)采集系統(tǒng)中，特別是在高速數(shù)據(jù)采集系統(tǒng)，該時鐘是一個非常重要的信號，不同時鐘抖動相差較大。當采集系統(tǒng)的輸入模擬信號帶寬較大時，在計算采集系統(tǒng)的信噪比時鐘抖動不能被忽略。量化噪聲的因素也需要考慮“1，12位的ADC，當輸入信號的頻率為40 MHz時，信噪比和采樣時鐘抖動曲線如圖3所示，橫坐標為對采樣時鐘抖動，y坐標為采集系統(tǒng)的信噪比。從

11、圖3中可以看出，為使ADC的采集系統(tǒng)的信噪比大</p><p><b>　　圖3</b></p><p>　　2.3高速數(shù)據(jù)緩存模塊</p><p>　　高速ADC數(shù)據(jù)存儲由A1tera公司生產的Cyclone FPGA芯片控制。如圖4的邏輯結構</p><p>　　數(shù)據(jù)采集系統(tǒng)使用MICRON公司的2片MT48LC4M

12、16A2SDRAM并聯(lián)作為系統(tǒng)的片上存儲器。并聯(lián)SDRAM內存位寬為32位，16 MB的容量，100 MHz的時鐘頻率。比的SRAM芯片的SDRAM的芯片具有更高的工作速度，容量更大，為系統(tǒng)提供了設計的靈活性。為了改善的SDRAM的傳輸帶寬，SDRAM控制器突發(fā)長度（burst length)設為8，這個突發(fā)長度是除整頁的讀/寫的最大突發(fā)長度。從高速12位ADC過來100MHz的信號在觸發(fā)使能信號有效時，由存寫控制模塊把ADC數(shù)據(jù)流的位

13、寬擴展l倍，擴展后的24比特采樣數(shù)據(jù)寫入FIF0中。當存儲器讀控模塊檢測到在FIF0存儲數(shù)據(jù)深度得到大于8時，從剩余的FIFO 8個24bit位的數(shù)據(jù)讀出，并使用wishbone（WB）14總線將數(shù)據(jù)傳送到SDRAM控制器，由SDRAM控制器把該數(shù)據(jù)寫入到外部的SDRAM芯片。雖然外部SDRAM芯片的數(shù)據(jù)總線寬度為32位，但實際使用只有24位，也就是理論上的SDRAM總線傳輸帶寬為300 MB /秒?？紤]到SDRAM的刷新和突發(fā)傳輸開銷

14、，實際上可以實現(xiàn)200MB / s，而ADC的采樣數(shù)據(jù)傳輸帶寬為1</p><p>　　2.4數(shù)據(jù)傳輸和觸發(fā)模塊</p><p>　　使用AMCC公司的PCI主控器件s5933傳輸采樣數(shù)據(jù)到計算機的內存中。 S5933是一種特殊的功能非常強大的，靈活運用PCI總線的控制器芯片。它完全符合PCI局部總線規(guī)范2.1l，不僅可以做PCI總線從設備，并且可以做PCI總線主設備進行數(shù)據(jù)傳輸。 S59

15、33擁有三個接口：PCI總線接口，ADDON總線接口和外部NVRAM參數(shù)配置界面。 PCI總線接口和連接到該PCI總線的計算機的插槽相連。計算機與用戶端可以通過ADDON總線接口的FIF0通道、PATH—THRU通道進行相互通信。PCI總線通過使用PATH . THRU渠道實現(xiàn)和客戶信息的交互。客戶端利用FIFO通道把本地存儲數(shù)據(jù)通過計算機的PCI總線傳遞到計算機內存中。計算機使用S5933的PASS。TRU操作控制FPGA的內部寄存器

16、。當計算機發(fā)出的PCI地址落在PASS—THRU定義的某個區(qū)中時，s5933通過PTATN向FPGA的PATH—TRU控制及譯碼邏輯發(fā)出請求。PATH—TRU控制與譯碼邏輯根據(jù) PTADR信號判斷本次操作是PATH-TRU讀操作還是寫操作，利用PTADR信號獲取本次PATH—THRU操作的地址信息(該</p><p>　?。?）根據(jù)計算機收集到的模擬信號最大數(shù)值，通過數(shù)控增益DAC寄存器使ADC的模擬信號輸入是接

17、近全振幅。</p><p>　?。?）通過ADC采樣時鐘寄存器設定ADC采樣時鐘工作（如果使用內部時鐘頻率）。</p><p>　　（3）設置ADC需要收集數(shù)據(jù)的總量：數(shù)據(jù)總量為32位的寄存器，足以滿足現(xiàn)有的雷達系統(tǒng)的需要，總數(shù)據(jù)寄存器必須是16的倍數(shù)。</p><p>　　（4）通過模式配置寄存器設置ADC高速數(shù)據(jù)采集系統(tǒng)的操作模式：設置ADC的外部觸發(fā)信號觸發(fā)模

18、式（電平觸發(fā)或邊沿觸發(fā)），設置ADC采樣信號的軟件觸發(fā)或硬件觸發(fā)（即外部觸發(fā)），可以控制ADC采樣。</p><p>　?。?）設置觸發(fā)延遲時間：雷達系統(tǒng)的采樣時間觸發(fā)延時可以通過寄存器進行設置</p><p>　　根據(jù)觸發(fā)模塊觸發(fā)條件，采樣的數(shù)據(jù)量和單次觸發(fā)采樣數(shù)量產生觸發(fā)使能信號，該信號相當于存FIF0寫使能信號。</p><p>　　計算機使用S5933的 P

19、CI主模塊FIF0通道實現(xiàn)采樣數(shù)據(jù)到計算機內存的自動傳輸。s5933內部的FIF0通道寫操作由FPGA完成，讀操作由s5933內部控制器完成。一旦檢測到S5933 WRFULL信號（F1F0信道滿信號）是無效的，或PCI主模塊寫FIF0通道不滿時，則從非空傳雙時鐘FIFO讀取數(shù)據(jù)，并寫入到S5933的PI主模塊的寫FIFO的數(shù)據(jù)通道。</p><p>　　高速緩存塊數(shù)記錄SDRAM控制器里面有多少數(shù)據(jù)塊要發(fā)送，在

20、寫入數(shù)據(jù)的一個塊中，SDRAM的高速緩存塊數(shù)上升1，當讀取從SDRAM數(shù)據(jù)的一個塊，高速緩存塊是減去1。 傳雙時鐘FIFO的寫控制由傳讀控制邏輯完成。傳讀控制邏輯，傳雙時鐘FIFO的寫控制由傳讀控制邏輯完成。傳讀控制邏輯只有在采集數(shù)據(jù)沒有傳輸完畢且傳雙時鐘FIF0非滿時，才啟動wb讀總線操作，從SDRAM緩沖區(qū)讀取一個數(shù)據(jù)塊并把該數(shù)據(jù)塊寫入傳雙時鐘FlF0中。</p><p>　　wishbone總線仲裁模塊實現(xiàn)

21、wb寫總線與wb讀總線的仲裁，其采用固定優(yōu)先級的方式，wb寫總線的優(yōu)先級比wb讀總線的優(yōu)先級高，保證了采樣數(shù)據(jù)的實時本地存儲。</p><p><b>　　3.軟件設計</b></p><p>　　為了提高數(shù)據(jù)傳輸速率，并降低了CPU資源占用，數(shù)據(jù)采集是通過使用PCI主動控制方式來實現(xiàn)數(shù)據(jù)到計算機內存的傳輸。然而由于S5933芯片單次傳輸數(shù)據(jù)的最大數(shù)量64 MB，，所

22、以如果你想連續(xù)發(fā)送大于64 MB的數(shù)據(jù)，則需要多次啟動主模式數(shù)據(jù)傳輸。在數(shù)據(jù)傳輸?shù)倪^程中，CPU不進行過程控制。軟件首先執(zhí)行PCI總線掃描，獲得S5933芯片占用 PCI配置的空間地址，然后向操作系統(tǒng)申請用于收集數(shù)據(jù)被傳遞到計算機的存儲器的物理空間，并且將該地址映射到s5933PCI主設備的物理空間。然后軟件配置S5933芯片內部寄存器，包括DMA傳輸數(shù)據(jù)量和PCI總線傳輸特性等寄存器，并且可以使s5933PCI主控操作。 S5933等

23、待FPGA發(fā)送采集數(shù)據(jù)，如果S5933內置寫FIFO芯片的通道不為空，則發(fā)起PCI總線操作把數(shù)據(jù)傳遞到計算機內存中。軟件根據(jù)實際雷達需求通過s5933的PASS-TRU操作對FPGA內部相關寄存器進行配置，設置數(shù)據(jù)采集系統(tǒng)相關參數(shù)，并觸發(fā)使能FPGA數(shù)據(jù)。雷達信號的數(shù)據(jù)采集和存儲由硬件自動完成，當采樣數(shù)據(jù)到達S5933單次數(shù)據(jù)傳輸量時，S5933向計算機申請一個中斷。軟件在中斷處理程序</p><p><b

24、>　　4性能分析與測試</b></p><p>　　在本文中，數(shù)據(jù)采集系統(tǒng)的采樣頻率為25兆赫到100兆赫，可以動態(tài)地按1兆Hz步長進行調整。采集系統(tǒng)來支持多個外部觸發(fā)模式，外部觸發(fā)方式由可編程邏輯器件動態(tài)設計。板卡內置的32 MB內存儲器決定了有用信息的采集時間，在采樣頻率100兆赫時，有用信息獲取時間可以達到160 ms.</p><p>　　該采集系統(tǒng)可實時傳輸?shù)臄?shù)

25、據(jù)量受可編程邏輯器件寄存器的大小的和計算機內存的大小限制，該系統(tǒng)采用了32位寄存器，能夠傳輸?shù)臄?shù)據(jù)理論總量為個采樣點，即6 GB。。</p><p>　　設計的數(shù)據(jù)采集系統(tǒng)經過測試，PCI傳輸速度是60 MB / s的（多次DMA數(shù)據(jù)傳輸），在100兆赫的工作頻率下為了實現(xiàn)雷達信息的實時采集，雷達系統(tǒng)的掃描周期與有用信息采集時間之比應該大于2.5。本系統(tǒng)涉及的雷達有用信息采樣時間為72μs，雷達掃描周期為360

26、us，因此，在本文中，高速數(shù)據(jù)采集系統(tǒng)能夠滿足雷達系統(tǒng)的實時存儲和傳輸?shù)男枨?。測試表明，該系統(tǒng)信噪比超過55分貝（30兆赫的模擬信號），該雷達系統(tǒng)能夠滿足需求的性能。</p><p><b>　　5 .結束語</b></p><p>　　在本文中，根據(jù)雷達信號的特性來完成高速數(shù)據(jù)采集系統(tǒng)的設計。該系統(tǒng)可以完成實時雷達信號的采集和存儲，該系統(tǒng)的SNR性能達到了雷達的需求

27、。由于采用可編程邏輯器件，所以該系統(tǒng)能夠滿足其他場合的需要。</p><p><b>　　參考文獻</b></p><p>　　[1] 張?zhí)N玉、王元祥、胡修林．高速數(shù)據(jù)采集系統(tǒng)中的存儲瓶頸問題及其解決[J]．微計算機應用，2007，28(6)：610—613．</p><p>　　[2]張俊杰，喬 崇，劉尉悅，等．高速數(shù)據(jù)采集系統(tǒng)時鐘抖動研究[

28、J]．中國科學技術大學學報，2005，35(2)：227—231．</p><p>　　[3]Dalt N D．on the Jitter Requirements of the Sampling Clock for Analog-t0-Digital Conveners[J]．IEEE Transactions on circuits and systems，2002，49(9)：1354-1360．<

29、;/p><p>　　[4]陳雙燕，王東輝·張鐵軍，等．基于WISHBONE的可兼容存儲器控制器設計[J]·計算機工程，2006，32(18)：240-242．</p><p>　　[5]張平，劉寄，伍衛(wèi)華·基于s5933的高速數(shù)據(jù)采集卡控制設計[J]．重慶大學學報，2006，29(10)：69—73．</p><p>　　High spee

30、d data acquisition system design</p><p>　　Zhang Jun Jie .Zhang Yi Feng. Ye Jia Jun</p><p>　　(Special optical fiber and optical access to the ministry of education key laboratory of Shanghai univ

31、ersity,Shanghai 200072)</p><p>　　Abstract: to meet the requirements of radar signal acquisition, design a 12 bit100 Ms/s data collection system based on PCI bus. The system can realize 6 GB of data real-time

32、 collection and storage. Programmable logic devices to control data collection, storage and transmission. PCI data transmission using PCI main mode, transmission rate reached 60 MB/s, the signal-to-noise ratio of the sig

33、nal collected at 55 dB (30 MHz analog signals).</p><p>　　Key words: the PCI controller; Programmable device; jitter.</p><p><b>　　Summarize</b></p><p>　　With the rapid de

34、velopment of communication, radar, and other fields, to deal with analog signal bandwidth and dynamic range is more and more big, the DAC sampling speed and precision demand is higher and higher. High speed and high prec

35、ision data gathering the required memory bandwidth is becoming more and more big, therefore, how to improve the data memory bandwidth has become one of the bottleneck of high-speed data acquisition system design. </p&

36、gt;<p>　　Radar system requirements of data acquisition system clock sampling frequency is 100 MHZ, at least for at least 10 bit DAC points frequency. While the existing computer system satisfies the requirement of

37、 the real-time transmission of radar system. But radar signal useful information make up only a small part of them. As shown in figure 1, therefore, as long as the collection and storage of useful information can realize

38、 the real-time radar signal samples storage.</p><p><b>　　figure 1</b></p><p>　　According to the characteristics of radar signal collection and storage, this paper designed a 12 bit10

39、0 Ms/s of the data acquisition system. The system USES the PCI bus are connected to the computer, the large capacity data acquisition system by using the interface card information useful for real-time information proces

40、sing, data acquisition system external signal control.</p><p>　　2. Framework, Data acquisition card</p><p>　　The whole collection system is divided into the following four parts: Part analog sig

41、nal modulation, The clock processing module, Data caching module, Data transmission and trigger module. As shown in figure 2.</p><p><b>　　figure 2</b></p><p>　　2.1 Analog signal mod

42、ulation</p><p>　　Analog signal modulation, including: before the analog signals and signal numerical control gain, and single side slip distribution. Analog signal pre op-amp input signal of the impedance ma

43、tching is realized by using AD9631 low-pass filtering and signal. In a radar system, scanning the target and radar stations from different collected radar signal amplitude is different, and in order to improve the signal

44、-to-noise ratio of the acquisition system, should make the simulation of the ADC input sig</p><p><b>　　2.2 RTC</b></p><p>　　In order to increase the acquisition system's flexibi

45、lity and universality, the ADC sampling clock chip can be from an external clock, also can from the internal clock. The choice of the sampling clock is decided by the board jumper wire device. Through a SMA connector is

46、connected to the external clock collection on the board, the external clock signal into TTL level, due to the ADC sampling clock need to PECL level, therefore the external clock by TTL to PECL level conversion chip MClOE

47、Ll6 sel</p><p><b>　　figure 3</b></p><p>　　2.3 High speed data cache module</p><p>　　High-speed ADC data storage is a Cyclone FPGA chip by A1tera company control. Logica

48、l structure as shown in figure 4</p><p><b>　　figure 4</b></p><p>　　Data acquisition system using MT48LC4M16A2SDRAM parallel 2 tablets up to MICRON company as a system of on-chip memo

49、ry. Parallel SDRAM memory bits wide is 32 bit, the capacity of 16 MB, the clock frequency of 100 MHz. Than SRAM chip SDRAM chips have higher working speed, larger capacity, provides more flexibility for system design. In

50、 order to improve the transmission bandwidth of SDRAM, the breaking length of SDRAM controller (burst length) at eight The burst length is in addition to the full pa</p><p>　　2.4 Data transmission and trigg

51、er module</p><p>　　Using AMCC company s5933 PCI master devices transmit the sampled data to a computer's memory. S5933 is a kind of special function is very strong, flexible use of PCI bus controller chi

52、p. It completely conforms to the PCI local bus specification 2.1 l, from already can do PCI bus device, and can do PCI bus master device for data transmission. S5933 have three interfaces: PCI bus interface, ADDON bus in

53、terface and external NVRAM parameters configuration interface. The PCI bus interface and the com</p><p>　　Computer using s5933 PASS. TRU operation control of the FPGA internal registers. When computer PCI ad

54、dress on PASS - THRU define a zone, s5933 to the PATH of the FPGA - through PTATN TRU and decoding logic control request. PATH - TRU and decoding logic control according to determine the operating PATH - PTADR signals TR

55、U to read or write operation, using PTADR signal to obtain the PATH - THRU operating address information (the address stored in s5933 PATH - TRU internal registers). The FPGA usin</p><p>　　Computer using s59

56、33 PASS. TRU operation control of the FPGA internal registers. When computer PCI address on PASS - THRU define a zone, s5933 to the PATH of the FPGA - through PTATN TRU and decoding logic control request. PATH - TRU and

57、decoding logic control according to determine the operating PATH - PTADR signals TRU to read or write operation, using PTADR signal to obtain the PATH - THRU operating address information (the address stored in s5933 PAT

58、H - TRU internal registers). The FPGA usin</p><p>　　(1) according to the biggest computer to analog signals collected, through nc gain DAC register ADC input analog signal input is close to full amplitude.&l

59、t;/p><p>　　(2) through the ADC sampling clock registers set ADC sampling clock working (if using the internal clock frequency.</p><p>　　(3) set the ADC to gather the amount of data: data volume for

60、 32-bit registers, enough to meet the needs of the existing radar system, the total data registers must be a multiple of 16.</p><p>　　(4) through the pattern configuration register setting the operation mode

61、 of the ADC high-speed data acquisition system: set up the ADC external trigger signal trigger mode (level trigger or edge-triggered), set up the ADC sampling signals to trigger software or hardware trigger (that is, the

62、 external trigger), can control the ADC sampling.</p><p>　　(5) sets the trigger delay period: radar system the trigger delay time of sampling time can be set through the register </p><p>　　Trigg

63、er module according to the trigger condition, the number of sampling data amount and single trigger sampling trigger enabling signal, the signal is equivalent to save FIF0 write enable signal.</p><p>　　Compu

64、ter using s5933 PCI main module FIF0 channel automatic transmission to realize sampling data to the computer's memory. S5933 FIF0 channel within the write operations performed by FPGA, the read operation performed by

65、 internal controller s5933. Once detected s5933 WRFULL transcription control module (F1F0 channel full signals) is invalid, or PCI main module to write FIF0 channels is not full, the double clock FIFO reads data from the

66、 airborne, and the data written to the s5933 PI main module</p><p>　　Cache block number record SDRAM controller inside how much a data block to be transmitted, in to write a block of data, the SDRAM cache bl

67、ock number l, when read a block of data from SDRAM, cache blocks is minus l. Double clock FIFO capacity of 2 KB, rate matching and data buffer implementation, speaking, reading and writing. Preach dual clock FIFO write c

68、ontrol by read complete control logic. The read only in data transmission to complete control logic and the double clock FIF0 is not full to l</p><p>　　Wishbone bus arbitration module realizes the wb write b

69、us and wb bus arbitration, and read it with the method of fixed priority, wb write bus priority than wb read bus priority, guarantee the real-time sampling data stored locally.</p><p>　　Software design</p

70、><p>　　In order to improve data transmission rate and reducing the number of CPU resources, data acquisition is realized by using PCI master way of data to the computer's memory. However because of s5933 si

71、ngle chip 64 MB, the maximum amount of data transferred so if you want to Continuous transmission is larger than 64 MB of data, then need to start the main mode data transmission for many times. In the process of data tr

72、ansmission, the CPU does not carry on the process control. Software to perform PC</p><p>　　4 Performance analysis and testing</p><p>　　In this paper, the data acquisition system sampling freque

73、ncy for 25 MHz to 100 MHz, can be dynamically adjusted by l MHz step length. Acquisition system to support multiple external trigger mode, the external trigger mode by the dynamic design of programmable logic device. Boa

74、rd built-in 32 MB on chip memory determines the useful information collection time, under the sampling frequency 100 MHZ, useful information acquisition duration can achieve 160 ms.The acquisition system can real-time tr

75、an</p><p>　　Design of data acquisition system is tested, the transmission speed PCI is 60 MB/s (multiple DMA data transmission), under the l00 MHz operating frequency, in order to achieve real-time data acqu

76、isition of radar information radar system scan cycles and the ratio of the useful information collection time should be greater than 2.5. This system involves the sampling time is 72 mu s useful information radar, radar

77、scanning cycle is 360 us, therefore, in this paper, the high-speed data acquisition s</p><p><b>　　5 TAG</b></p><p>　　In this paper, according to the characteristics of the radar sig

78、nal to complete the design of high-speed data acquisition system. This system can accomplish real-time radar signal acquisition and storage, the system SNR performance achieve the demand of the radar. Due to using progra

79、mmable logic devices, so the system can meet the needs of other occasions. </p><p>　　References </p><p>　　[1] Zhang Yunyu, Wang Yuanxiang, Hu Xiulin. High-speed data acquisition syst

80、em of storage bottleneck problem and its solution[J]．Microcomputer Applications，2007，28(6)：610—613．</p><p>　　[2]Zhang Junjie, Joe chung, LiuWei yue, etc. High speed data acquisition system clock jitter[J]．Jo

81、urnal of university of science and technology of China，2005，35(2)：227—231．</p><p>　　[3]Dalt N D．on the Jitter Requirements of the Sampling Clock for Analog-t0-Digital Conveners[J]．IEEE Transactions on circ

82、uits and systems，2002，49(9)：1354-1360．</p><p>　　[4]Chen Shuangyan, wang donghui Zhang Tiejun, etc. Based on the WISHBONE compatible memory controller design[J]·computer engineering，2006，32(18)：240-242．&