CMOS高速折疊插值型模數(shù)轉(zhuǎn)換器的IC設(shè)計(jì).pdf

1、上海大學(xué)碩士學(xué)位論文CMOS高速折疊插值型模數(shù)轉(zhuǎn)換器的IC設(shè)計(jì)姓名：蔡俊申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：電工理論與新技術(shù)指導(dǎo)教師：徐美華20040201AbstractThepurposeofthisprojectistorealizeadesignofa8bithigh—speedanalog—todigitalConverter(ADQWiththefastdevelopmentofcomputertechnologydigitalproc

2、essingtechnologyandmicroelectmnictechnologyadvantagedelectronicsystemsarepresentedcontinuallyThedesignofanalog—todigitalconverterscontinuestobecriticalinthedevelopmentofmixedsignalintegratedcircuitsforavarietyofapplicati

3、onsthatprocessandtransmit、，oiceandvideosignalsandstillimageNewprocessesandapplicationscontinuetodemandtheresearchanddevelopmentoftheseblocksAftercomparingwithmanystmctrutesofADC，thefoldingand—interpolatingarchitectureiss

4、electedWithakindofnovelhighspeedcomparatorandwelldesignedfoldingamplifiers，highspeedandlowpowerareachievedThefolding—andinterpolatingconverterdescribedinthethesisusecontinuous—time￡nalogcircuitstocreate”folded”signalthat

5、reducethenumberofcomparatorsrequiredIoraflashADCtypeconversioninasingleclockcycleandleadingtoareductionincomponentcost，areaandpowerTocompensateforthefoldingamplifiernon—linearities，twofoldingamplifiersareusedintheanalog—

6、todigitalconvertdesignAnovelhighspeedcomparatoriselaboratedinthethesis，whichmeetstherequirementofspeedandaccuracyThisthesisdescribesthedesignoffolding—and—interpolatinganalog。。todigitalconvertersincludingthefunctionality

7、anddesignconstraintsforeachblockThewhole8bitCMOShighspeedfolding—andinterpolatinganalogto—digitalconverterisdesignedandsimulatedbyShang—hua06lamCMOSmodelTheconvertercanoperatenormallyupto150MSPSwhilethepowerconsumptionis