外文翻譯---借助dds的精密頻率的一種替代方法

1、<p><b>　　畢業(yè)設(shè)計(jì)說明書</b></p><p><b>　　英文文獻(xiàn)及中文翻譯</b></p><p>　　學(xué)生姓名： 學(xué)號(hào)： </p><p>　　學(xué) 院： </p>&

2、lt;p>　　專 業(yè)： </p><p>　　指導(dǎo)教師： </p><p>　　2012年 6 月</p><p>　　An alternative method of precise frequency by the aid o

3、f a DDS</p><p><b>　　Contents</b></p><p>　　A method of frequency measurement based on a closed loop composed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (DD

4、S) is presented in this paper. The DDS serves as reference sinewave signal generator acting at one of the FC's inputs. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency. From the co

5、mparison of the two signals a logic output that controls an up/down counter is produced. The counter's output acting as the Frequency Setting Wo</p><p>　　1 Introduction</p><p>　　The most co

6、mmonly used frequency measurement technique adopts counters that count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, techniques where the pulses of a reference frequency

7、 are counted during one or more periods of the unknown one are also common. In the latter case, the period instead of the frequency is estimated .Some papers in [1] in the literature deal with the problem of low frequenc

8、y measurement and are focusing in the frequency r</p><p>　　The above methods can be characterized as open-loop methods i.e. digital counters are used to count during a predefined tinle interval and calculate

9、 the result afterwards. Its closed-loop form characterizes the proposed method in this paper. By the term "closed-loop" we denote some sort of feedback. A waveform with a known (controlled) frequency is produce

10、d within the circuit and is fed back to the frequency comparison stage which consecutively forces it to approximate the unknown (input) freque</p><p>　　2 Direct Digital Synthesis</p><p>　　A typ

11、ical Direct Digital Synthesizer consists of a RAM containing samples of a sinewave (sine look-up table, LUT). These samples are swept in a controlled manner by the aid of a Frequency Setting Word (FSW), which determines

12、the phase step. A typical FSW is 32-bit wide, but 48-bit synthesizers leading in higher frequency resolution are also available. A phase accumulator produces the successive addresses of the sine look-up table and generat

13、es a digitized sine wave output. The digital part of th</p><p>　　The frequency of the output signal for an n-bit system is calculated in the following way; If the phase step is equal to one, the accumulator

14、will count by ones, taking clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolution. Setting

15、 the FSW equal to two, results in the accumulator counting by twos, taking clock cycles to complete one cycle of the output sinewave. It </p><p><b>　　fDDS=</b></p><p>　　fres= fclk/&

16、lt;/p><p>　　For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is 7.68 mHz. If n is increased to 48, with the same clock frequency, a resolution of 120 nHz is possible.</p>

17、<p>　　3 The proposed frequency measurement technique</p><p>　　The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise

18、 immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the D

19、DS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According t</p><p>　　3.1 Operation of the circuit</p><p>　　Th

20、e circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half of it's maximum. In

21、addition, the frequency step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximation the frequency step is divided by two and added or subtracted to the FSW of the DDS, depending on

22、the output of the Frequency Comparator. The approximation proc</p><p>　　The digital FSW, after the appropriate correction and decoding, is presented in an output device i.e. an LCD display or any other suita

23、ble means. Alternatively, it can be digitally recorded or it can be read by a computer. </p><p>　　As conclusion of this initial approach we could say that the proposed method is based on a Digital Controlled

24、 Synthesizer which is forced to produce a frequency almost equal to the unknown one.</p><p>　　3.2 Frequency comparison</p><p>　　The frequency comparator seems to be the most critical stage of t

25、he design. The implementation is based on a modified phase/frequency comparator proposed by Philips in the 74HC4046 PLL device. It consists primarily of two binary counters, counting up to two and an RS flip-flop.</p

26、><p>　　The function of the frequency comparator is based on the principle that the lower frequency, i.e. larger period, includes (embraces) at least one or more full periods of the higher frequency (smaller per

27、iod). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, the circuit operates as follows: When the first counter (#1) encounte

28、rs two rising edges of the unknown frequency in one period of the DDS, it set</p><p>　　At a first glance one could think that the synthesized frequency could reach the measured one (fin) and then the operati

29、on of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as "hysteresis&

30、quot;. Hysteresis depends on the initial timing relation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding</p><p>　　3.3 Interaction between fr

31、equency comparator and digital synthesizer</p><p>　　After the successive approximation of the unknown frequency the Frequency Comparator "realizes" that the synthesized frequency is higher (lower)

32、than the unknown one and produces a logic 0 (1) at the output which commands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the

33、 DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the </p><p>　　When DDS output (fDDS) has approached fin, due to hysteresis,

34、no specific frequency is synthesized. Instead, it swings between f1 and f2, where f1 and f2 are the two extreme values of the frequency swing lying symmetrically around fin. The DDS output can be considered as a frequenc

35、y modulated carrier by a triangular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a typical output of the Frequency Comparator. In the same figure, uppe&l

36、t;/p><p>　　3.4 Description of the prototype hardware</p><p>　　For evaluation purposes two prototypes have been built and tested in the laboratory. The first approach was a low frequency instrument

37、 (operating up to 15 KHz) . The purpose of this implementation was to study the principles of operation of the proposed method. Next, a higher frequency prototype was built which will be described in more detail here. In

38、 order to implement the digital part of the prototype, (Frequency Comparator, Successive Counter, Correction Stage) two PLD devices from Altera (E</p><p>　　The generated sinewave has upper harmonics, due to

39、the DAC operation. These harmonics are removed from the filters that follow the DAC. The correction stage is implemented partially on the PLDs and partially on the microcontroller. Based on the up-down command of the fre

40、quency comparator we store the two extreme values, FSW1 and FSW2, which are then transferred into the micro-controller (Atmel AT89C52), transformed into numerical representation and fed to the LCD Display. The micro-cont

41、roller al</p><p>　　The behaviour of the instrument was according to the expected and was alike to a conventional bench frequency counter. The speed of measurement was checked using lower trace, obtained by t

42、he aid of a digital oscilloscope. Each state, high or low, of this waveform corresponds to the time required for one measurement.</p><p>　　4 Conclusion</p><p>　　In this paper an alternative met

43、hod of frequency measurement has been proposed. It has been pointed out that in most cases this method is faster than conventional methods for the same frequency resolution. On the other hand, the precision of the method

44、 can be very high due to the inherent high frequency resolution characteristic of the DDS that is employed. This synthesizer, which can be thought as an oscillator, is driven to "oscillate" in the region of the

45、 unknown input frequency. A comparison</p><p>　　The second major advantage of this method is that if repetitive frequency measurements are to be taken, the instrument remains locked and the frequency measure

46、ment does not restart from the beginning, but instead is automatically driven to lower or higher values. In other words, the loop has the capability to follow the changes in the frequency of the input signal. In the conv

47、entional counting techniques the counting procedure is repeated (restarted) for each new measurement.</p><p>　　Another important advantage is the noise immunity of the system, due to its closed loop nature.

48、A detailed study of the noise behavior has not been carried out in this paper. This is mainly because the aim of this text is to present an alternative principle of frequency measurement. Moreover, the final output of th

49、e system is taken after some further processing (measurement correction) which also contributes to the noise immunity.</p><p>　　借助DDS的精密頻率的一種替代方法</p><p>　　頻率測(cè)量的方法基于閉環(huán)組成,主要是一個(gè)頻率比較器(FC)和直接數(shù)字合成器(DD

50、S),對(duì)此在本文中進(jìn)行了介紹。DDS作為標(biāo)準(zhǔn)信號(hào)發(fā)生器在FC的投入之中扮演一定的角色。FC接受了DDS的硬限幅波形以及未知的頻率。從比較兩個(gè)信號(hào)的輸出，控制邏輯向上/向下計(jì)數(shù)器產(chǎn)生了。計(jì)數(shù)器的輸出頻率設(shè)定字（FSW）代理指示的DDS產(chǎn)生一個(gè)新的正弦波頻率接近未知之一。當(dāng)循環(huán)沉淀，頻率設(shè)定字給出了未知的高頻數(shù)字估計(jì)。優(yōu)勢(shì)是從DDS固有的高分辨率和環(huán)路噪聲免疫力而來，從而設(shè)計(jì)同樣精確和不受影響的頻率計(jì)。所有額外相關(guān)的階段都被儀器的顯示器顯示

51、出來。 </p><p><b>　　1簡(jiǎn)介</b></p><p>　　最常用的測(cè)頻技術(shù)采用計(jì)數(shù)在預(yù)定的時(shí)間窗口（光圈）的未知頻率的脈沖的計(jì)數(shù)器。此外，凡任何參考頻率的脈沖在一個(gè)或多個(gè)未知一期計(jì)算方法也很常見。在后一種情況下，代替頻率的周期只是估計(jì)的。本文獻(xiàn)的第[1]部分的某些文件處理了低頻率的測(cè)量問題并集中在心臟（心臟）信號(hào)的頻率范圍（幾赫茲）或在電源頻率（50-

52、60赫茲）。這些技術(shù)實(shí)際上是在測(cè)量訊號(hào)的時(shí)間，并使用一些方法來計(jì)算它的倒數(shù)，即頻率。在第[2]中，頻率由查找表的方法計(jì)算。其他[4-6]的內(nèi)容是關(guān)于微處理器或以微控制器為基礎(chǔ)的。上述方法的特點(diǎn)是開環(huán)方法，即數(shù)字計(jì)數(shù)器來計(jì)數(shù)在預(yù)定tinle間隔，之后計(jì)算結(jié)果。其閉環(huán)形式刻畫了本文提出的方法。這個(gè)術(shù)語“閉環(huán)”我們用來記一些反饋排序。一個(gè)已知（控制）的頻率波形在電路中產(chǎn)生，并反饋到強(qiáng)制它來接近未知的（輸入）的頻率的頻率比較階段。產(chǎn)生上述提及的

53、受控的頻率波形是一個(gè)直接數(shù)字合成器。 </p><p>　　2．直接數(shù)字頻率合成器</p><p>　　一個(gè)典型的直接數(shù)字頻率合成器包含一個(gè)正弦波（正弦查找表LUT）樣品的RAM。在限定相位跳躍的頻率設(shè)置字的控制方式下來搜尋這些樣本。一個(gè)典型的頻率設(shè)置字是32位寬，但48位合成器在較高的頻率分辨率也可使用。一個(gè)相位累加器產(chǎn)生連續(xù)的正弦查找表的地址，并生成一個(gè)數(shù)字正弦波輸出。DDS的數(shù)字部分

54、，即相位累加器和查表，被稱為數(shù)控振蕩器（NCO）。最后階段，這相對(duì)于前一個(gè)主要是模擬，包括一個(gè)D / A轉(zhuǎn)換器在一個(gè)過濾器之后。過濾器使數(shù)字化的正弦波更平穩(wěn)，生產(chǎn)連續(xù)輸出信號(hào)。在凡方波輸出需要的應(yīng)用中，這由一個(gè)硬限制器在經(jīng)過過濾器之后得到。這不等于使用例如蓄電池的，而不是硬過濾和波形輸出最高位有限，因?yàn)闀?huì)遇到很大的抖動(dòng)。對(duì)于n位系統(tǒng)的輸出信號(hào)的頻率是按以下方式計(jì)算的;如果相位步等于1，將累加器的計(jì)數(shù)加1，以時(shí)鐘周期，以滿足整個(gè)LUT和生

55、成一個(gè)周期的輸出正弦波。這是該系統(tǒng)能生成的最低的頻率，也是它的頻率分辨率。設(shè)置FSW為二，計(jì)數(shù)器的結(jié)果間隔數(shù)為二，以時(shí)鐘周期來完成一個(gè)周期的正弦波輸出。它可以很容易地表明，對(duì)于任意整數(shù)m，其中m <，所采取的時(shí)鐘周期數(shù)旨在產(chǎn)生一個(gè)輸出的正弦波周期/米，輸出頻率（fDDS）</p><p><b>　　fDDS=</b></p><p>　　fres= fclk/

56、</p><p>　　對(duì)于n = 32，有一個(gè)fclk = 33 MHz的時(shí)鐘頻率，頻率分辨率為7.68兆赫茲。如果n是增加至48個(gè)具有相同的時(shí)鐘頻率，分辨率為120 nHz是可能的。</p><p>　　3.被提議的頻率測(cè)量技術(shù) </p><p>　　產(chǎn)生我們目前的設(shè)計(jì)的想法來自DDS的頻率分辨率極高的設(shè)備并且由它的封閉循環(huán)的形式抗干擾執(zhí)行。一個(gè)（已知）頻率源，即

57、DDS，采用于一個(gè)閉環(huán)并且被迫逐步產(chǎn)生頻率等于未知輸入輸出。一個(gè)在DDS系統(tǒng)的經(jīng)驗(yàn)法則是可以接受的最大合成頻率為時(shí)鐘頻率的25％（遠(yuǎn)低于奈奎斯特限制）。根據(jù)這一點(diǎn)，我們的原型使用一個(gè)33 MHz的時(shí)鐘將有效地?cái)?shù)到8兆赫。在砷化鎵產(chǎn)品來看，我們可以看到，最近的DDS設(shè)計(jì)可以在高達(dá)400兆赫的時(shí)鐘頻率范圍運(yùn)作。因此，目前的方法，頻率計(jì)數(shù)器工作頻率達(dá)100 MHz是可以設(shè)計(jì)的。該決議將取決于FSW的數(shù)量和時(shí)鐘頻率。 DDS的時(shí)鐘頻率是非常重要

58、的，因?yàn)樗鼫p小，該方法的決議（定義為fclk /）更出色，即它變得更精細(xì)的改進(jìn)。時(shí)鐘頻率下降的影響是其最大輸出頻率，限制計(jì)數(shù)器的最大計(jì)數(shù)隨之降低。主要模塊已被證明。其中包括：頻率比較和DDS。為了克服特定頻率比較器的一些缺點(diǎn)校正階段已被納入。這一階段也可用于測(cè)量提取，以顯示正確的讀數(shù)。</p><p><b>　　3.1電路的操作</b></p><p>　　該電路工

59、作在一個(gè)新的測(cè)量DDS的輸出頻率會(huì)在一開始以逐次逼近的方法控制這樣一種方式。最初的DDS頻率將有一半為它的最大值。此外，該步驟將頻率近似等于 DDS的最大頻率的1/ 4。根據(jù)比較器輸出的頻率，在每一個(gè)近似值中頻率被分成兩個(gè)并且增加或減少到DDS的FSW中。在步長(zhǎng)下降到一時(shí)逼近過程停止。在此之后，向上/向下計(jì)數(shù)器替代逼近機(jī)制。在適當(dāng)?shù)男拚徒獯a后，數(shù)碼的FSW被顯示在在一個(gè)輸出設(shè)備中，即一臺(tái)液晶顯示器或任何其他合適的方式。或者，也可以進(jìn)行

60、數(shù)字記錄，也可以由計(jì)算機(jī)閱讀。由于這一初步的方法，我們可以說，被提議的方法是基于被迫產(chǎn)生和未知幾乎相等的頻率的數(shù)字控制合成器。</p><p><b>　　3.2頻率比較</b></p><p>　　頻率比較似乎是在設(shè)計(jì)中最關(guān)鍵的階段。該實(shí)現(xiàn)是基于一種改進(jìn)的相位/頻率比較器，由飛利浦在74HC4046 PLL設(shè)備中生產(chǎn)。它主要包括兩個(gè)二進(jìn)制計(jì)數(shù)器，共計(jì)兩個(gè)和一個(gè)RS觸

61、發(fā)器。頻率比較器的功能是基于頻率較低，即較大的時(shí)期的原則，包括（擁抱）至少有一個(gè)或多個(gè)頻率較高（小周期）完整周期。這意味著，兩個(gè)或兩個(gè)以上的較高頻率上升邊緣的波形在較低頻率周期內(nèi)。鑒于上述情況，電路操作如下：當(dāng)?shù)谝粋€(gè)計(jì)數(shù)器（＃1）在一個(gè)時(shí)期內(nèi)遇到DDS的兩個(gè)未知頻率的上升邊緣，它設(shè)置RS觸發(fā)器的輸出。RS觸發(fā)器的邏輯“1”在向上/向下計(jì)數(shù)器的U / D的控制輸出中起作用，強(qiáng)制DDS升高輸出頻率。相反，當(dāng)?shù)诙€(gè)計(jì)數(shù)器（＃2）在一個(gè)周期內(nèi)記

62、錄兩個(gè)未知的頻率的上升的DDS輸出的邊緣，它又恢復(fù)成RS觸發(fā)器的輸出的。這個(gè)動(dòng)作降低了DDS的頻率。乍一看人們可以認(rèn)為，合成頻率可達(dá)到實(shí)測(cè)（鰭），然后計(jì)數(shù)器停止運(yùn)作。不幸的是并非如此。一個(gè)充滿活力的機(jī)制代替了。該電路需要一些時(shí)間來實(shí)現(xiàn)正確的頻率的關(guān)系。我們將把這個(gè)時(shí)間稱為“遲滯”。遲滯取決于最初的DDS輸出時(shí)序關(guān)系和未知頻率。最初，在滯后期，有關(guān)更大的頻率的指示是不明確的，即它可以是錯(cuò)誤</p><p>　　3.

63、3頻率比較器和數(shù)字合成器之間的互動(dòng)</p><p>　　在頻率比較器“實(shí)現(xiàn)” 的未知頻率逐次逼近之后，合成的頻率較高（低）于未知，并在控制向上/向下計(jì)數(shù)器的輸出端產(chǎn)生計(jì)算向下(上)一個(gè)邏輯0（1）的方向。如前所述，這個(gè)計(jì)數(shù)器的輸出被認(rèn)為是從FSW到DDS的階段。在最初的DDS頻率低時(shí)，合成頻率將會(huì)逐步增加，達(dá)到未知之一。這不會(huì)通過頻率比較器“實(shí)現(xiàn)”和合成頻率將會(huì)在一些時(shí)鐘周期繼續(xù)增加，直到比較器檢測(cè)出它的兩個(gè)輸入

64、頻率的正確關(guān)系，未知的一方和DDS輸出。在相反（降低）的情況下，同樣的現(xiàn)象也將會(huì)被觀察到。這是因?yàn)榍懊嫣岬降臏笞饔谩．?dāng)DDS輸出（fDDS）已接近鰭，由于滯后性，沒有特定的頻率合成。相反，它搖擺于F1和F2之間，其中F1和F2是頻率對(duì)稱擺動(dòng)的兩個(gè)極端值。 DDS的輸出可以被看作是一個(gè)三角波形的頻率調(diào)制的載體。三角波形是FSW施加到DDS的模擬表示法。較低的形跡顯示一個(gè)比較典型的頻率輸出。在相同的圖上，上部的描繪，以模擬的形式顯示的FS

65、W的變化，這是因?yàn)樗髨D接近正確的值。利用輔助硬件電路這個(gè)波形已被俘獲：數(shù)字至模擬轉(zhuǎn)換器（DAC）連接到U / D轉(zhuǎn)換計(jì)數(shù)器（最高位），以研究操作的輸出。這款DAC不會(huì)顯示在電路的框圖中。下跟蹤的U </p><p>　　3.4原型硬件的描述</p><p>　　用于評(píng)估的目的，兩個(gè)原型在實(shí)驗(yàn)室已建成。第一種方法是一個(gè)低頻率的工具（工作達(dá)15千赫）。這次實(shí)施的目的是研究該原則的操作方法。接

66、下來，一個(gè)更高的頻率原型制造出來了，在此進(jìn)行更詳細(xì)的描述。為了使原型的數(shù)字部分（頻率比較，連續(xù)計(jì)數(shù)器，校正階段）生效，兩個(gè)產(chǎn)自Altera（EPF8064LC68 - 12）的 PLD器件被使用了。這些設(shè)備和由高通Q2240I - 3S1所生產(chǎn)DDS相互聯(lián)系。DDS具有32位輸入和一個(gè)12位輸出的正弦查找表（LUT）。該12位輸出的LUT送入到由模擬設(shè)備AD9713B發(fā)出的D / A轉(zhuǎn)換器中。其模擬輸出連接到I / V放大器（電流電壓轉(zhuǎn)

67、換器）。由于DAC工作，生成的正弦波具有較高的諧波。這些諧波在DAC之后將從過濾器刪除。這次調(diào)整階段一部分實(shí)施在PLD一部分在微控制器。基于頻率比較器的上下命令，我們存儲(chǔ)兩個(gè)極端值，F(xiàn)SW1和FSW2，然后再進(jìn)入微控制器Atmel AT89C52）轉(zhuǎn)換成數(shù)字表示并反饋到LCD顯示器。該微控制器還控制著整個(gè)運(yùn)作的原型。儀器的行為和預(yù)期的一樣，和常規(guī)的頻率計(jì)數(shù)器工作臺(tái)是一樣的。在數(shù)字示波器的幫助下，測(cè)量采用較低速度跟蹤檢查。每個(gè)狀態(tài)<

68、/p><p><b>　　4結(jié)論</b></p><p>　　在該文件中頻率測(cè)量的替代方法已經(jīng)提出。已經(jīng)被指明，在大多數(shù)情況下，對(duì)于相同頻率的解決方案，這種方法比傳統(tǒng)方法更快。另一方面，由于DDS的固有高頻率的特點(diǎn)，該方法的精度非常高。這種可作為振蕩器的合成器，在未知的輸入頻率范圍被驅(qū)使“振蕩”。與常規(guī)方法的比較已經(jīng)給出，兩個(gè)原型已建成并在實(shí)驗(yàn)室測(cè)試。這種方法的第二個(gè)主要

69、優(yōu)點(diǎn)是，如果重復(fù)頻率測(cè)量，工具一直鎖定，頻率測(cè)量不重新從頭開始，而是自動(dòng)驅(qū)使到更低或更高的值。換句話說，循環(huán)有能力按照輸入信號(hào)頻率的變化而改變。在傳統(tǒng)的計(jì)算技術(shù)里，計(jì)算過程為每個(gè)新的測(cè)量而重復(fù)（重新啟動(dòng)）。另一個(gè)重要優(yōu)勢(shì)是該系統(tǒng)的抗噪聲能力，由于其閉環(huán)的性質(zhì)。一個(gè)詳細(xì)的噪音行為的研究已經(jīng)在本文中指出。這主要是因?yàn)楸疚牡哪康氖且岢鲆粋€(gè)頻率測(cè)量的替代原理。此外，該系統(tǒng)的最終輸出采取了一些進(jìn)一步的（測(cè)量校正）有助于抗噪聲能力的后處理。<