外文翻譯---關(guān)于直接數(shù)字頻率合成器

1、<p>　　All About Direct Digital Synthesis</p><p>　　What is Direct Digital Synthesis? </p><p>　　Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—

2、by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies

3、, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little pow</p><p>　　Why would on

4、e use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies? </p><p>　　The ability to accurately produce and control waveforms of various frequencies and profiles h

5、as become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency st

6、imulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations. </p><p>　　Figure 1. The AD9833-a one-chip waveform generator.</p

7、><p>　　Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog co

8、nverter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and indu

9、strial applications because single-chip IC devices can generate programmable </p><p>　　Furthermore, the continual improvements in both process technolog y and design have resulted in cost and power consumpti

10、on levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operating at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.</p>

11、;<p>　　What are the main benefits of using a DDS? </p><p>　　DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to genera

12、te simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined

13、with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an ext</p><p>　　What kind of outputs can I generate with a typical DDS de

14、vice? </p><p>　　Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS.</p><p>　　DDS devices are not limited to purely sinusoidal outputs. Figure 2 shows the square-, triangular-, and

15、 sinusoidal outputs available from an AD9833.</p><p>　　How does a DDS device create a sine wave? </p><p>　　Here’s a breakdown of the internal circuitry of a DDS device: its main components are a

16、 phase accumulator, a means of phase-to-amplitude conversion (often a sine look-up table), and a DAC. These blocks are represented in Figure 3.</p><p>　　Figure 3. Components of a direct digital synthesizer.&

17、lt;/p><p>　　A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binar y number programmed into the frequency register (tuning word). &l

18、t;/p><p>　　The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up t

19、able, which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fix

20、ed-frequency sine wave, a constant value (the phase increment—which is determined</p><p>　　What do you mean by a complete DDS? </p><p>　　The integration of a D/A converter and a DDS onto a singl

21、e chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI. </p><p>　　Let’s talk some more about the phase accumulator. How does it work? </p><p>　　Contin

22、uous-time sinusoidal signals have a repetitive angular phase range of 0 to 2.The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS imple

23、mentation.</p><p>　　To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to t

24、he equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel,

25、 at a constant speed, results in one complete cycle of the output sine wave. The phase accumu</p><p>　　The phase accumulator is actually a modulo- M counter that increments its stored number each time it rec

26、eives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip aroun

27、d the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points c</p><p><b>　　where: </

28、b></p><p>　　fOUT = output frequency of the DDS </p><p>　　M = binary tuning word </p><p>　　fC = internal reference clock frequency (system clock) </p><p>　　n = length

29、 of the phase accumulator, in bits </p><p>　　Changes to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-lo

30、cked loop. </p><p>　　As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output

31、 waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform a

32、nd permitting filtering on the output. </p><p>　　When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. </p

33、><p>　　Then how is that linear output translated into a sine wave? </p><p>　　A phase -to - amplitude lookup table is used to convert the phase-accumulator’s instantaneous output value (28 bits for

34、AD9833)—with unneeded less-significant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10 -bit) D/A converter. The DDS architecture exploits the symmetrical nature of a si

35、ne wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup </p><p><b>　　Figure 5.</b></p>

36、;<p>　　關(guān)于直接數(shù)字頻率合成器</p><p>　　什么是直接數(shù)字頻率合成器？</p><p>　　直接數(shù)字頻率合成器（DDS）是一種通過產(chǎn)生一個(gè)以數(shù)字形式時(shí)變的信號(hào)，然后執(zhí)行由數(shù)字至模擬轉(zhuǎn)換的方法。由于DDS設(shè)備的操作主要是數(shù)字的，它可以提供快速解決輸出頻率之間切換，優(yōu)點(diǎn)是具有精細(xì)的頻率以及運(yùn)行頻率范圍廣泛。由于設(shè)計(jì)方面和工藝技術(shù)的進(jìn)步，如今DDS器件已變得非常緊湊而

37、且功率非常小。</p><p>　　為什么要使用直接數(shù)字頻率合成器（DDS）？難道沒有其它方法使不同頻率和配置文件能夠很容易地產(chǎn)生頻率？</p><p>　　能夠準(zhǔn)確地產(chǎn)生和控制波形已經(jīng)成為一些行業(yè)的主要要求。無論是提供低相位噪聲的雜散性能良好的可變頻率通信，還是只需在生成的頻率上激活工業(yè)或生物醫(yī)學(xué)檢測(cè)設(shè)備的應(yīng)用程序，成本低是重要的設(shè)計(jì)考慮。</p><p>　　設(shè)

38、計(jì)師以相位鎖定回路（PLL）為基礎(chǔ)，需要非常高的頻率合成技術(shù)，以動(dòng)態(tài)規(guī)劃的數(shù)字到模擬的轉(zhuǎn)換器（DAC）來產(chǎn)生許多可能產(chǎn)生的頻率，但DDS技術(shù)迅速獲得了解決頻率（或波形）產(chǎn)生和工業(yè)應(yīng)用要求的方法，因?yàn)閱涡酒呻娐菲骷梢援a(chǎn)生簡(jiǎn)單的可編程的模擬輸出高分辨率和準(zhǔn)確性的波形。</p><p>　　此外，在這兩個(gè)過程中不斷改進(jìn)技術(shù)和設(shè)計(jì)，使成本和功耗水平前所未有的低。例如AD9833，一個(gè)基于DDS的可編程波形發(fā)生器（圖

39、1），工作電壓5.5V與25MHz的時(shí)鐘，消耗的最大功率為30mW。</p><p>　　圖1 AD9833波形發(fā)生器</p><p>　　使用DDS有什么主要好處？</p><p>　　對(duì)DDS的AD9833器件進(jìn)行編程，如通過一個(gè)高速串行外設(shè)接口（SPI），而且只需要一個(gè)外部時(shí)鐘來生成簡(jiǎn)單的正弦波。DDS器件現(xiàn)已可以產(chǎn)生從1到400MHz的頻率，（時(shí)鐘基于10

40、3MHz兆赫）。電源效益低，成本低，包裝單小，加上其固有的優(yōu)良性能，并能夠以數(shù)字形式（和重新編程）輸出波形使DDS器件是極具吸引力的解決方案，相比不太靈活的包括分子聚合離散在內(nèi)的解決方案。</p><p>　　一個(gè)典型的DDS的設(shè)備可以產(chǎn)出什么樣的輸出？</p><p>　　DDS器件不僅限于純粹的正弦波輸出。圖2顯示了方波、三角波和正弦波輸出。</p><p>　

41、　圖2 DDS輸出的矩形波-三角波-正弦波</p><p>　　如何使用DDS的設(shè)備創(chuàng)建一個(gè)正弦波？</p><p>　　這里有一個(gè)DDS的內(nèi)部電路：其主要成分是相位累加器，振幅轉(zhuǎn)換（通常是正弦查找）和一個(gè)DAC。這些模塊的代表圖如圖3。</p><p>　　圖3 組件的直接數(shù)字合成器</p><p>　　DDS產(chǎn)生一個(gè)特定頻率的正弦波。它

42、的頻率取決于兩個(gè)變量，參考時(shí)鐘頻率和（控制字）數(shù)字編程的頻率。</p><p>　　二進(jìn)制數(shù)的頻率主要輸入到相位累加器。在使用正弦查找表時(shí)，用相位累加器計(jì)算一個(gè)階段（角）的地址查找表，輸出幅度的數(shù)字值對(duì)應(yīng)相位角的正弦。反過來，DAC把這個(gè)數(shù)字轉(zhuǎn)換為相應(yīng)值的模擬電壓或電流。要生成一個(gè)固定頻率的正弦波，恒定值（相位增量，這是由二進(jìn)制數(shù)決定）被添加到時(shí)鐘周期的相位累加器。如果相位增量大，相位累加器會(huì)迅速通過正弦查找表，

43、從而產(chǎn)生高頻率的正弦波。如果相位增量小，相位累加器將采取更多的步驟，因而產(chǎn)生較慢的波形。</p><p>　　完整的DDS是什么意思？</p><p>　　D/A轉(zhuǎn)換器和一個(gè)DDS的單一芯片的整合通常被稱為一個(gè)完整的DDS的解決方案，ADI公司的普通性質(zhì)DDS。讓我們說些有關(guān)累加器的知識(shí)。它是如何工作的？連續(xù)時(shí)間正弦信號(hào)的角度范圍內(nèi)有一個(gè)重復(fù)的階段0至2。數(shù)字的實(shí)施沒有什么不同，該計(jì)數(shù)器

44、可以把相位累加器作為DDS的功能來執(zhí)行。</p><p>　　為了理解這一點(diǎn)的基本功能，將可視化的正弦波振蕩作為一個(gè)階段輪圍繞旋轉(zhuǎn)圓向量（見圖4）。每個(gè)階段輪指向?qū)?yīng)的等效點(diǎn)1波周期的正弦。由于矢量旋轉(zhuǎn)的輪子，形象化的角度的正弦值產(chǎn)生相應(yīng)的正弦波。一個(gè)車輪周圍的相速度向量，為一個(gè)常數(shù)，正弦波輸出結(jié)果為一個(gè)完整周期。相位累加器提供等距相角值隨車輪周圍的向量線性旋轉(zhuǎn)。相位累加器對(duì)應(yīng)于點(diǎn)的波周期輸出的正弦。</p

45、><p>　　相位累加器實(shí)際上是一個(gè)模- M的計(jì)數(shù)器，每次收到一個(gè)時(shí)鐘脈沖其存儲(chǔ)的數(shù)量遞增。遞增幅度取決于輸入字（米）。這個(gè)字形成相位步長(zhǎng)之間的參考，它有效地設(shè)置跳過多少分左右相輪。規(guī)模越大的跳躍，相位累加器以越快的速度溢出，且其周期相當(dāng)于一個(gè)正弦波。該輪在數(shù)字離散相點(diǎn)中，取決于分辨率的相位累加器（n），這決定了DDS的調(diào)諧。對(duì)于一個(gè)n = 28位相位累加器，1 ... 0001 M值的0000會(huì)導(dǎo)致相位累加器溢出后

46、228參考時(shí)鐘周期（增量）。如果M值更改為0111 ... 1111，相位累加器溢出后，將只有2參考時(shí)鐘周期（取決于奈奎斯特最低要求）。這種關(guān)系是發(fā)生在基本調(diào)整方程DDS的結(jié)構(gòu)為：</p><p>　　其中：FOUT是DDS的輸出頻率</p><p>　　M是頻率控制字的二進(jìn)制</p><p>　　fC是內(nèi)部參考時(shí)鐘頻率（系統(tǒng)時(shí)鐘）</p><p

47、>　　n是每組長(zhǎng)度的相位累加器位，</p><p>　　M的值發(fā)生變化導(dǎo)致輸出頻率的變化。無回路的建立時(shí)間發(fā)生在一個(gè)循環(huán)鎖相內(nèi)。由于輸出頻率的增加，減少樣本周期數(shù)。</p><p>　　由于抽樣理論決定了至少兩個(gè)周期，每樣都需要重建的輸出波形，基本的DDS輸出頻率是fC/2。</p><p>　　然而，對(duì)于實(shí)際應(yīng)用中，輸出頻率是有限的，在一定程度改善波形質(zhì)量的

48、重建，并允許濾波輸出。當(dāng)產(chǎn)生一個(gè)恒定的頻率，相位輸出線性增加，因此模擬波形生成本身就是一個(gè)斜坡。</p><p>　　試問，線性輸出波形怎樣轉(zhuǎn)化為正弦波？</p><p>　　A相方法-振幅查找表用于轉(zhuǎn)換相位累加器的瞬時(shí)輸出值（28比特AD9833）將正弦波振幅信息，提交（10位）到D/A轉(zhuǎn)換器。DDS的結(jié)構(gòu)充分利用了正弦波對(duì)稱的性質(zhì)和利用的一個(gè)映射邏輯合成一個(gè)完整周期的正弦波。該相位對(duì)振