外文翻譯--st7536介紹

1、<p>　　ST7536 introduce</p><p>　　By Joel HULOUX</p><p>　　I- INTRODUCTION TO THE ST7536</p><p>　　The ST7536 is a half duplex synchronous FSK-modem,and has been designed to operat

2、e on powerline networks.For a complete communication system, a micro-controller and a powerline-interface (PLI) are needed (see Figure 1).Such a system is able to transmit and receive on 4 different channels with 2 diffe

3、rentdata rates (600 and 1200 baud).The baudrate (BRS) and channel (CHS) selection is made,according to the Table.</p><p>　　The ST7536 is a half duplex modem,as it has two operation modes;receive or transmit

4、data.The mode selection is made with a Rx/Tx control input.Data input and output are related to the clock signal;it’s a synchronous modem. This clock signal is generated by the ST7536.Only a few external components have

5、to be added for full operation of the ST7536:a crystal, four resistors and five capacitors.</p><p>　　II- ST7536 DESCRIPTION</p><p>　　The ST7536 is a single chip modem;all the electrical circuits

6、 needed for a complete modem are inside the chip. The modem is available in 28 pins PLCC (see Figure 2).In transmit mode the Transmit Data (TxD) is sampled on the positive edge of the clock (CLR/T).Then the data enters t

7、he FSK modulator. The frequency on which this modulator operates is set by the time base and control logic. In normal operation the multiplexer(MUX) selects the FSK modulator signal to be send to the transmit filter.Thi&

8、lt;/p><p>　　The powerlines on which the modem has to operate, have variations in their line characteristics,which are very frequent and totally unpredictable.The automatic level control uses a feed back signal

9、(ALCI) from the powerline interface to adjust the transmit output (ATO).In receive mode the signal enters the chip on the Receive AnalogInput(RAI).</p><p>　　The received signal is filtered in the receive ban

10、d-pass filter. It’s just like the transmit filter,a switched capacitor filter.The automatic frequency control is used to set it on the right frequency. After being amplified the signal is down converted and filtered in t

11、he intermediate frequency band-pass filter.The resulting signal is sent to the FSK demodulator. The coupling of the intermediate frequency filter output (IFO) to the FSK DEModulator Input(DEMI) is made by an externalcapa

12、citor whic</p><p>　　A clock recovery circuit extracts the receive clock (CLR/T) from the demodulated output (RxDEM) of the FSK demodulator. Synchronous received data (RxD) is delivered on the positive edge o

13、f the clock.A time base section delivers all the internal clock signals from a crystal oscillator running at 11.0592MHz.The crystal is connected between the XTAL1 and XTAL2 pins.It is also possible to provide directly a

14、 clock signal on XTAL1 instead of using a crystal.To debug the chip and test external circuit</p><p>　　III- ST7536 PIN DESCRIPTION</p><p>　　The pin description is not given in numerical order,bu

15、t the pins are described in relation with their function and consequentlysometimes with other pins.</p><p>　　- power supply input</p><p>　　- channel selection</p><p>　　- crystal osc

16、illator input</p><p>　　- AFCF stabilisation</p><p>　　- automatic level control input</p><p>　　- data input and output</p><p>　　- test inputs</p><p>　　- IFO

17、/DEMI output/input</p><p>　　- transmit output and receive input</p><p>　　- Rx/Tx control input</p><p>　　- reset input</p><p>　　III.1- Power Supply Input</p><

18、p>　　- Pin 8 (DGND): Digital ground (0V)</p><p>　　- Pin 9 (DVDD): Digital positive supply voltage (+5V)</p><p>　　- Pin 18 (DVSS): Digital negative supply voltage (-5V)</p><p>　　-

19、Pin 21 (AVSS): Analog negative supply voltage (-5V)</p><p>　　- Pin 22 (AGND): Analog ground (0V)</p><p>　　- Pin 23 (AVDD): Analog positive supply voltage (+5V)</p><p>　　Internally t

20、he ST7536 has separated power supplies:The digital andanalog circuit sare separated.Externally the power supplies should be connected together.For decoupling,both the positive and negative supplies are decoupled with 2 c

21、apacitors.C6 and C7 decouple the positive,C8 and C9 the negative supplies.For proper operation the digital positive supply voltage should be decoupled with a capacitor(C10)mounted close to Pin9.C6,C8 and C10 are100nF/16V

22、ceramic capacitors,C7 and C9 10uF/16V tant alcap</p><p>　　III.2 - Channel Selection</p><p>　　- Pin 15 (CHS): Channel selection input</p><p>　　- Pin 16 (BRS): Baudrate selection inpu

23、t</p><p>　　Both inputs are digital inputs (0/+5V). The ST7536 operates with two bit rates: 600 and 1200 baud. These bit rates are selected with pin 16 (BRS). For both bit rates the ST7536 offers two channels

24、,which are selected with pin 15 (CHS).Alogical”0” is represented by 0V, a”1”by +5V. R1 and R2 are pull-down resistors,creating a logical”0”.Closing a switch gives a”1”.The selection is made according to Table 1.</p>

25、;<p>　　III.3 - Crystal Oscillator Input</p><p>　　- Pin 13 (XTAL2): Crystal oscillator output</p><p>　　- Pin 14 (XTAL1): Crystal oscillator input</p><p>　　The internal crystal

26、 oscillator of the ST7536 needs an external crystal. This one should be a 11.0592MHz crystal. Two capacitors (C1 and C2) have to be added for proper operation. They are typically 22pF/10V ceramic capacitors. It is also p

27、ossible to connect directly a clock signal to the oscillator input, in this case the crystal and the capacitors should be removed.On the application board this option is notused. The ST7536 clock signal is the time refer

28、ence of the system.</p><p>　　III.4 - AFCF Stabilisation</p><p>　　- Pin 17 (AFCF) : Automatic frequency control output</p><p>　　In the ST7536 an automaticcontrol section adjusts the

29、central frequency of the receive and transmit band-passfilters. The stabilityof this sectionhas to be ensured with an external RC network.</p><p>　　III.5 - Automatic Level Control Input</p><p>　

30、　Pin 27 (ALCI): Automatic level control input. </p><p>　　The output stage of the transmit path consists of an automatic level control (ALC).It offers the possibility to keep the output voltage of the power a

31、mplifier independent of variations of the powerline network. The impedance of these networks can be anywhere in the range of 5-100.If the impedance of the powerline changes,the outputof theamplifier will change.With the

32、ALC input it is possible to correct these output variations. To control the output of the powerline interface a feed-back signal i</p><p>　　The automatic level control can decrease the maximum transmit outpu

33、t in 32 steps of 0.84dB. The gain range is 0dB-26dB. A peak detection is done on the signal presented on the ALC Input and the ALCcompares it to two reference voltages, VT1 (1.87V) and VT2 (2.12V).</p><p>　　

34、If max. VALCI < VT1 the next gain is increased by 84dB.</p><p>　　If VT1 < max. VALCI <VT2 there is no gain change.</p><p>　　If VT2 < max. VALCI the next gain is decreased by 0.84dB.&

35、lt;/p><p>　　The gain of the feed-back amplifier is such that the feed-back signal peak voltage falls between VT1 and VT2.</p><p>　　III.6 - Data Input and Output</p><p>　　- Pin 5 (RxD):

36、 Synchronous receive data output</p><p>　　- Pin 6 (CLR/T): Receive and transmit clock</p><p>　　- Pin 7 (RxDEM): Demodulated data output</p><p>　　- Pin 12 (TxD): Transmit data input&

37、lt;/p><p>　　The ST7536 is a synchronous modem; data input and output are related to the clock (CLR/T). In transmit mode the ST7536 generates this clock signal. The transmit data are sampled on the positive edge

38、 of CLR/T. Therefore the TxD should be valid at that moment.In receive mode the demodulated (receive) data is available at pin 7(RxDEM). A clock recovery circuit extracts the clock signal from the demodulated data and de

39、livers synchronous data (RxD) on the positive edge of CLR/T. On the application bo</p><p>　　III.7 - Test Inputs</p><p>　　- Pin 3 (TEST4): Test input,with a”1”on this pin the multiplexer selects

40、thetransmit band-pass filter input(TXFI).</p><p>　　- Pin 4 (TEST3): Test input which gives a direct acces to the clock recovery circuit.This input is selected when TEST1=”1”.</p><p>　　- Pin 10 (

41、TEST1): Test input,a”1”on this pin cancels the automatic switching from transmit to receive mode, and validates the TEST3 input to the clock recovery circuit.</p><p>　　- Pin 11(TEST2): Test input,a”1”on this

42、 pin reduces the automatic switching time (from transmit to receive mode) to 1.48ms.On the applicationboard TEST 2/3/4 are not used,and Pins 3, 4, and 11 are thereforeset at 0V.With a switch TEST1 can be set at”0”or”1”.S

43、ee also the Rx/Tx control input.</p><p>　　III.8- IFO/DEMIOutput/Input</p><p>　　- Pin 19 (IFO): Intermediate frequency filter output</p><p>　　- Pin 20 (DEMI): FSK demodulator input&l

44、t;/p><p>　　The connection between the intermediate frequency filter output and the FSK demodulator input should be made externally with a capacitor (C5, 1uF/10V).</p><p>　　III.9 - Transmit Output a

45、nd Receive Input</p><p>　　- Pin 24 (RAI): Receive analog input</p><p>　　- pin 28 (ATO): Analog transmit output</p><p>　　Pin 24 is the receive input of the ST7536. The receive output

46、 of the powerline interface should be connected to this pin.The maximum input voltageis 2VRMS. The receive sensitivity of the ST7536 is 2mVRMS on channel 1 and 2 (600 baud),and 3mVRMS on channel 3 and 4 (1200 baud).Pin 2

47、8 is the transmit output of the ST7536. The transmit input of the powerline interface should be connected to this pin. The ATO output is regulated by the ALCI circuit. The maximum output voltage is 3.5VPP. The second ha&

48、lt;/p><p>　　III.10 - Rx/Tx Control Input</p><p>　　Pin 1 (Rx/Tx): Receive or transmit mode selection input .</p><p>　　The ST7536 is a half duplex modem and has therefore two operation m

49、odes: receive and transmit. This mode selection is done with the Rx/Tx input. The transmit mode is selected when Rx/Tx is”0”.If Rx/Tx is held a”0”longer than 3 seconds, the ST7536 switches back to receive mode. To set th

50、e ST7536 again in transmit mode, Rx/Tx should be held at”1”for a minimum of 3s before being set to”0”.The carrier activation time is 1msec. To be able to observe the transmit output of the ST7536 on the power line</p&

51、gt;<p>　　III.11 - Reset Input</p><p>　　- Pin 2 (RESET): Logic reset and power-down input </p><p>　　When this input is set at”0”the ST7536 is in power-down mode.All the internal logic is t

52、hen reset.For normal operation this input should be set</p><p>　　at”1”.On the application board this input is controlled by the micro-controller.</p><p>　　Technical Data Sheet SSC P300 PL Networ

53、k Interface Controller Features</p><p>　　-Enables Low-cost CEBus compatible products</p><p>　　-EIA-600 (CEBus) Data Link Layer services</p><p>　　-EIA-600 Physical Layer transceiver&

54、lt;/p><p>　　-Spread Spectrum Carrier Power Line technology</p><p>　　-SPI Host Processor interface</p><p>　　-Data Link, Controller, and Monitor modes</p><p>　　-Single +5 Vo

55、lt power supply requirement</p><p>　　-20 pin SOIC package</p><p>　　Introduction</p><p>　　The Intellon SSC P300 PL Network Interface Controller is a highly integrated power line tran

56、sceiver and channel access interface for implementing CEBus compatible products.The SSC P300 provides the Data Link Layer (DLL) control logic for EIA-600 channel access and communication services, a Spread Spectrum Carri

57、er(SSC) power line transceiver, signal conditioning circuitry, and a serial peripheral interface (SPI) compatible host interface. A minimum of external circuitry is required to connect the</p><p>　　The inher

58、ent reliability of SSC signaling technology and incorporation of basic Data Link functionality combine to provide substantial improvement in network and communication performance over other power line communication metho

59、ds. The SSC P300 also makes an excellent low cost network interface for twisted pair and DC power systems. A typical CEBus power line node using the SSC P300 is illustrated below.</p><p>　　SSC P300 Node Bloc

60、k Diagram</p><p>　　VDD DC Supply Voltage -0.3to 7.0V</p><p>　　VIN Input Voltage at any Pin VSS-0.3 to VDD+0.3V</p><p>　　TSTG Storage Temperature -65 to +150C</p><p>　　T

61、L Lead Temperature(Soldering,10 seconds)300C</p><p><b>　　Note:</b></p><p>　　Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. This device contains

62、 protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages.</p><p&g

63、t;　　Recommended Operating Conditions</p><p>　　VDD DC Supply Voltage 4.5、5.0、5.5V</p><p>　　FOSC Oscillator Frequency 12 +/- 0.01% MHz</p><p>　　TA Operating Temperature -40、+25、+85C&l

64、t;/p><p>　　Humidity non-condensing</p><p>　　Electrical Characteristics</p><p>　　Conditions:VDD = 4.5 to 5.5 V T=-40 to +85C</p><p>　　Symbol Parameter Min Typical Max Units

65、</p><p>　　VOH Minimum High-level Output Voltage 2.4V</p><p>　　VOL Maximum Low-level Output Voltage (1) 0.4V</p><p>　　VIH Minimum High-level Input Voltage 2.0V</p><p>　　

66、VIL Maximum Low-level Input Voltage 0.8V</p><p>　　Hys Minimum Input hysteresis 350 mV</p><p>　　IIL Maximum Input Leakage Current +/-10A</p><p>　　vSO SSC Signal Output Voltage (2) 4

67、VP-P</p><p>　　IDD Total Power Supply Current 25 mA</p><p>　　Latchup (3) 150 mA</p><p><b>　　Notes:</b></p><p>　　1. IOL = 2 mA</p><p>　　2. ZL = 2

68、K || 10 pF</p><p>　　3. JEDEC JC -40.2</p><p>　　SSC PL P300 Network Interface Controller</p><p>　　SSC P300 Pin Assignments</p><p>　　1 4MHZ 4 MHz clock out 4 MHz clock ou

69、tput available for host microcontroller.</p><p>　　2 CS*Chip select Digital input, active low. Enables serial peripheral interface.</p><p>　　3 VSSD Digital ground Digital ground reference.</p&

70、gt;<p>　　4 XIN Crystal input Connected to external crystal to excite the IC’s internal</p><p>　　oscillator and digital clock.</p><p>　　5 XOUT Crystal output Connected to external crystal

71、to excite the IC’s internal oscillator and digital clock.</p><p>　　6 VDDD Digital supply 5.0 VDC +/- 10% digital supply voltage with respect to VSSD.</p><p>　　7 INT* Interrupt Digital output, ac

72、tive low. Attention request to host</p><p>　　microcontroller.</p><p>　　8 SCLK SPI data clock Serial peripheral interface clock input from host</p><p>　　microcontroller.</p>&

73、lt;p>　　9 SDO SPI data out Data output to host microcontroller serial peripheral interface. SDO is`tristate when CS* is false.</p><p>　　10 SDI SPI data in Data input from host microcontroller serial periph

74、eral</p><p>　　interface.</p><p>　　11 TS Tristate Active low digital output signal driven from the same internal</p><p>　　signal that enables the output amplifier.</p><p&g

75、t;　　12 RST* Reset Active low digital input.</p><p>　　13 VSSA Analog ground Analog ground reference.</p><p>　　14 SO Signal output Analog signal output. Tristate enabled with internal TS signal.&l

76、t;/p><p>　　15 C2 Capacitor 2 Connection for 680pF capacitor to ground.</p><p>　　16 C1 Capacitor 1 Connection for 680pF capacitor to ground.</p><p>　　17 SI Signal input Analog signal in

77、put.</p><p>　　18 VDDA Analog supply 5.0 VDC +/- 10% analog supply voltage with respect to VSSA.</p><p>　　19 TP0 Test point 0 Reserved pin for testing.</p><p>　　20 VSSD Digital groun

78、d Digital ground reference.SSC PL P300 Network Interface Controller</p><p>　　SSC P300 Node Overview</p><p>　　The SSC P300 is designed to meet the needs of products requiring EIA-600 compatibilit

79、y. As the SSC P300 uses fewer interface signals than the SSC P400 does, a lower cost host (microcontroller) may be used. Coupling the lower cost host with the low cost of the SSC P300, an EIA-600 compliance node can be a

80、dded to cost sensitive products. The SSC P300 can transmit and receive all four Data Link services defined in the EIA-600 standard, which allows the designer to select the best Data Link service </p><p>　　Da

81、ta Link functions and Physical layer services of the protocol. Specific DLL services include transmission and reception of packets, byte-to-symbol conversion for transmitted packets, symbol-to-byte conversion for receive

82、d packets, transmit channel access (based on packet priority and EIA-600 access rules), and CRC generation and checking. The last section is the power line analog functions. These functions include: coupling the signal f

83、requencies onto the medium, amplification of the transmitt</p><p>　　1. Initialization routine.</p><p>　　2. Routine to write commands out to the chip.</p><p>　　3. Routine to read dat

84、a from the chip.</p><p>　　4. Interrupt service routine.</p><p>　　The SSC P300 can be placed into one of three operating modes:Data Link Layer (DLL) mode, Controller(CON) mode,and Monitor(MON) mo

85、de. In the DLL mode, the P300 will manage all address matching, and timer resources.In the CON mode, the P300 converts the incoming signal into bytes.It becomes the responsibility of the host to manage address matching a

86、nd timer resources. The MON mode monitors the medium. Any packet detected on the medium is passed up to the host regardless of the packet’s address or </p><p><b>　　ST7536介紹</b></p><p&g

87、t;　　Joel HULOUX著</p><p>　　1、ST7536 的介紹</p><p>　　ST7536是一個半雙工同步FSK調(diào)制解調(diào)器,并且對于設(shè)計和操作電力線網(wǎng)絡(luò)是很有幫助的。對于一個完整的通信系統(tǒng),微型控制器和電力線接口(PLI)是必要的。這樣系統(tǒng)能在4種不同頻道上以2種不同的數(shù)據(jù)率(600和1200波特)傳送和接收信號。波特率(BRS)和頻道(CHS)選擇在此時被執(zhí)行。&l

88、t;/p><p>　　ST7536是一個半雙工調(diào)制解調(diào)器,因為它有二個操作方式，接收或傳送數(shù)據(jù)。模式選擇用Rx/或用Tx作為控制輸入。數(shù)據(jù)輸入和輸出是與時鐘信號有關(guān)的。它是一個同步調(diào)制解調(diào)器。這個時鐘信號由ST7536所引起。幾個外在分組都必須增加對ST7536的進行設(shè)置:一個晶振, 四個電阻器和五臺電容器。</p><p>　　2、ST7536 描述</p><p>

89、　　ST7536是一個具有唯一一個芯片的調(diào)制解調(diào)器；所有電子電路需要有一個完整的調(diào)制解調(diào)器處在芯片里面。調(diào)制解調(diào)器是在28個串口可利用的PLCC。傳送數(shù)據(jù)的方式(TxD)被抽樣在時鐘的正面邊緣(CLR/T)。然后數(shù)據(jù)進入FSK調(diào)制器。這個調(diào)制器所需的頻率被設(shè)置在時間基準和控制邏輯上。在正常運行多重通道(MUX)選擇的FSK調(diào)制器信號是送到傳送過濾器的。過濾器是一臺被交換的電容器帶通濾波器。時間基準和控制邏輯的用途是所謂的自動頻率控制(A

90、FC)的設(shè)置。這過濾器以傳送頻率, 對應(yīng)于選擇的頻道，在過濾以后,傳輸信號被送到自動電平控制(ALC)電路。這種控制的使用是為了克服有線的問題阻抗變異。</p><p>　　調(diào)制解調(diào)器必須運用在電力線耦合下來的信號,變異的出現(xiàn)是在于他們的線性特征發(fā)生改變,有些是非常頻繁而且是完全變化莫測的。自動電平控制使用一個反饋信號(ALCI) 從電力線接口調(diào)整傳送信號(ATO)。在接收信號進入芯片時分析其輸入的方式(RAI)

91、。接收的信號通過接收帶通濾波器進行過濾。它就像傳送過濾器, 等效于電容過濾器。自動頻率控制使用設(shè)置它在正確的頻率。在被放大以后信號是在轉(zhuǎn)換和過濾下通過中頻帶通濾波器。收到的信號寄發(fā)到FSK解調(diào)器。中頻過濾器輸出信號的聯(lián)結(jié)(IFO)對FSK 解調(diào)器輸入(DEMI)由均勻集合電壓做改變。</p><p>　　時鐘補救電路時鐘(CLR/T)是從被解調(diào)的輸出信號提供的。同步被接收的數(shù)據(jù)(RxD)被設(shè)置在正面時鐘的邊緣。時

92、間基本的部分提供所有內(nèi)部時鐘信號從一臺晶體控制振蕩器提供并運行在11.0592MHz。晶振是運行于XTAL1和XTAL2 之間。它還可能直接地從XTAL1提取時鐘信號而不是使用晶振。調(diào)試芯片和測試外部ST7536提供一些測試選擇。傳送帶通濾波器直接通過過濾器被觀察。這輸入(TxFI) 由多重通道選擇在TEST4=1。接收帶通濾波器輸出信號(RxFO)被設(shè)置在串口25。最后時鐘補救可能被設(shè)置在TEST1=1。TEST3輸入在這種情況下直接

93、根據(jù)輸入時鐘設(shè)置。</p><p>　　3、ST7536 PIN 描述</p><p>　　串口的描述不需要數(shù)字次序,但串口在與其他串口之間的聯(lián)系被描述。</p><p><b>　　- 電源輸入</b></p><p><b>　　- 頻道選擇</b></p><p>　　

94、- 晶體控制振蕩器輸入</p><p><b>　　- AFCF平穩(wěn)</b></p><p>　　- 自動電平控制輸入</p><p><b>　　- 數(shù)據(jù)輸入和輸出</b></p><p><b>　　- 測試輸入</b></p><p>　　- IF

95、O/DEMI輸出輸入</p><p>　　- 傳送輸出和接收輸入</p><p>　　- Rx/Tx控制輸入</p><p><b>　　- 重新設(shè)置輸入</b></p><p><b>　　3.1 電源輸入</b></p><p>　　- Pin 8 (DGND): 數(shù)字式

96、接地(0V)</p><p>　　- Pin 9 (DVDD): 數(shù)字式正極供應(yīng) 電壓(+5V)</p><p>　　- Pin 18 (DVSS): 數(shù)字式負極供應(yīng) 電壓(-5V)</p><p>　　- Pin 21 (AVSS): 模式負極供應(yīng) 電壓(-5V)</p><p>　　- Pin 22 (AGND): 模式接地(0V)<

97、;/p><p>　　- Pin 23 (AVDD): 模式正極供應(yīng)電壓(+5V)</p><p>　　ST7536內(nèi)部分離了電源:數(shù)字式分析電路被分離。外部電源應(yīng)該一起被連接。正極和負極供應(yīng)與2臺電容器分離。C6和C7由正極供應(yīng),C8和C9負性供應(yīng)。適當?shù)牟僮鲾?shù)字式正極電源電壓應(yīng)該被分離。C6,C8和C10是100nF/16V的電容器,C7 和C9 是10mF/16的電容器。</p>

98、;<p><b>　　3.2 頻道的選擇</b></p><p>　　PIN15（CHS）：頻道選擇輸入</p><p>　　PIN16（BRS）：波特率選擇輸入</p><p>　　以上的兩種輸入都是數(shù)字輸入（0/+5V）。這個ST7536設(shè)置在兩種比特率上：（600和1200BAUD）。這些比特率是由PIN16（BRS）來選擇

99、的。對于兩種比特率ST7536通過PIN15提供兩種頻道。非邏輯0通過0V來描述，而非邏輯1是通過+5V來描述的。R1和R2是被電阻器來隔離的，創(chuàng)造一個邏輯0，而關(guān)閉給予的非邏輯1。</p><p>　　3.3 晶體振蕩器的輸入</p><p>　　Pin 13(XTAL2):晶體振蕩器輸出</p><p>　　Pin 14（XTAL1）:晶體振蕩器輸入</p

100、><p>　　國內(nèi)的ST7536晶體振蕩器需要一個外部的晶振。它需要一個11.0592MHZ晶體。電容器（C1和C2）需要另外合適的設(shè)置。它們是具有代表性的瓷介電容器。如果晶體和電容器被分離它可能直接連接一個時鐘信號到振蕩器的輸入?；谶@種需求這種選擇是不被使用的。這種ST7536時鐘信號是對系統(tǒng)時間的提及。</p><p>　　3.4 AFCF的描述</p><p>

101、　　PIN 17（AFCF）：自動頻率控制的輸出。在ST7536自動控制部件會調(diào)整接收和傳輸?shù)倪厧盘柕闹行念l率。這種部件的穩(wěn)定性必須由一個外部的RC網(wǎng)絡(luò)來保證。</p><p>　　3.5 自動電平控制輸入</p><p>　　- Pin 27(ALCI): 自動電平控制輸入。傳送通路的輸出階段包括自動電平控制(ALC)。它提供保留功率放大器的輸出電壓的獨立電力線網(wǎng)絡(luò)變異的可能性。這些網(wǎng)

102、絡(luò)阻抗可能是任何在范圍的5-100W。如果電力線的阻抗改變,輸出電壓則變動。對于ALC的輸入根據(jù)輸出的變化范圍而改變?？刂齐娏€的輸出連接的反饋信號是需要的。這個信號被送往自動增益控制放大器。</p><p>　　自動電平控制能減少最大傳送輸出信號值在32步每0.84dB。增益范圍是0dB 到-26dB。高峰檢測是對于在ALC上的現(xiàn)值信號輸入和ALC來比較兩種電壓范圍。VT1(1.87V)與VT2(2.12V)。

103、</p><p>　　如果最大。VALCI<VT1下增益被增加0.84dB。</p><p>　　如果VT1<最大。VALCI<VT2增益是沒有改變。</p><p>　　如果VT2<最大。VALCI下增益被減少0.84dB。</p><p>　　反饋放大器的增益是這樣，反饋信號峰頂電壓下跌到VT1與VT2之間<

104、/p><p>　　3.6 數(shù)據(jù)輸入和輸出</p><p>　　- Pin 5 (RxD): 同步接收數(shù)據(jù)輸出信號</p><p>　　- Pin 6 (CLR/T): 接收和傳送時鐘</p><p>　　- Pin 7 (RxDEM): 被解調(diào)的數(shù)據(jù)輸出</p><p>　　- Pin 12 (TxD): 傳送數(shù)據(jù)輸入&l

105、t;/p><p>　　ST7536是一個同步調(diào)制解調(diào)器；數(shù)據(jù)輸入和輸出與時鐘有關(guān)(CLR/T)。在傳送方式下ST7536產(chǎn)生這個時鐘信號。傳送數(shù)據(jù)被抽樣在CLR/正面邊緣T。所以TxD應(yīng)該在那片刻是有根據(jù)的。在接收被解調(diào)的方式(接受)數(shù)據(jù)是可利用的在串口7 (RxDEM)。 時鐘補救電路從被解調(diào)的數(shù)據(jù)提取時鐘信號和提供同步數(shù)據(jù)(RxD)基于CLR/ 正面邊緣T。在應(yīng)用模式RxDEM數(shù)據(jù)輸出沒被使用。所有數(shù)據(jù)信號對于S