0.18μmcmos工藝622mhz電荷泵鎖相環(huán)設計

1、哈爾濱理工大學碩士學位論文0.18μmCMOS工藝622MHz電荷泵鎖相環(huán)設計姓名：郭喜俊申請學位級別：碩士專業(yè)：微電子學與固體電子學指導教師：殷景華20090301哈爾濱理工人學工學碩I：學位論文Designof622MHzCPPLLbasedon018pmCMOStechnologyAbstractPhaselockedloop(PLL)isacircuitthatcanlettheoutputsignalbesynchlonous

2、withthereferencesignalinfrequencyorphaseIthasbeendevelopedfromlinearanalogPLLwithpoorperformancetomodemdigitalandanalogdigitalhybridPLL、)~rithmghperformanceandhasbeenwidelyusedinelectronics，communicationandinstrumentsCha

3、rgepumpPLL(CPPLL)hastheadvantages，suchassmalllockedphasedifferenceand、忻decapturerangeSOithasbeenthemainPLLproductamongnumerousPLLtechnologiesACPPLLthatCanbeusedtotheSDHsystemoffibercommtmicationhasbeenimplementedbYuS噸the

4、0181amCMOStechnologyThecenterfrequencyofthe灑putandoutputsignalsoftheproposedPLLale155MHzand622MHzrespectivelyTheproposedPLLCanbeusedinthetwovelocitylevelsofSTM1andSTM4oftheSDHsystemACPPLLconsistsFrequency／Phasedetector(P

5、FD)，chargepump(CP)，lowpassfilter(LF)，voltagecontrolledoscillator(vco)，andfrequencydividerCPisthekeyunitoftheCPPLL，itdecidestheCPPLLsperformancetoalargeextentThereismismatchbetweenchargeanddischargecurrentinCPaimingatsolv

6、ingthemismatchproblemanovelgainboostingstructureisdesignedTheproposedstructurecangreatlyimprovetheCP’SoutputresistanceandreducethechannellengthmodulationeffectSOitCanincreasethematchperformanceobviouslyTheeffectofnoiseCa

7、nbereducedthrou曲adoptingthedifferentialringstructure，linearrangecallbeenlargedbyadoptingsymmetricload，andswitchingrateCanbeboostedbyadoptingpositivefeedbackOthermodulesareoptimized砧lthefunctionalmodulesoftheCPPLLandthesy